Design of differential TG based 8T SRAM cell for ultralow-power applications

Roy, Chandramauleshwar; Islam, Aminul

doi:10.1007/s00542-018-4035-7

Cited by 20 publications

(19 citation statements)

References 38 publications

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“…This is attributed to an increase in mobility of charge carriers which further increase the write current and improve the write delay. In addition to this, the write access time of LP9T SRAM cell is improved by 1.09×,2.09×,1.63×,2.85×,2.04× as compared to DF8T [21],TG8T [26],PCF10T [18],SPG11T [20] and LP12T [19] SRAM cells respectively. It occurs because of increased write word line voltage which strengthens N2 and N3 transistors.…”

Section: Read/write Access Timementioning

confidence: 97%

“…It happens due to the quadratic relationship between the supply voltage and power dissipation. Further, the read power consumption of LP9T SRAM cell is decreased by 1.41×,1.40×, 1.39×,1.33×,1.38×,1.40× as compared to Conv.6T [28],DF8T [21],TG8T [26],PCF10T [18],SPG11T [20],LP12T [19] SRAM cells respectively. It is because of single sided read structure that minimizes the read bit-line capacitance.…”

Section: Read/write Power Dissipationmentioning

confidence: 99%

“…The write power consumption at different supply voltages has seen in Fig.7 (c). It has indicated that the write power of the LP9T SRAM cell is decreased 2.1×,3.64×, 2.06×,1.96×,4.23×,2.45× as compared to Conv.6T [28],DF8T [21],TG8T [26],PCF10T [18],SPG11T [20],LP12T [19] SRAM cells respectively. This happens due to the weaken of pull-up path through PMOS (P1 and P2) transistors.…”

Section: Read/write Power Dissipationmentioning

confidence: 99%

“…Fig.8(a) shows the time of read access which considered SRAM topologies at various supply voltages value. It is noticed that the LP9T SRAM cell, read access time has been improved by 2.72×,2.5×,3.55×,8.15×,3.49×,5.56× as compared to Conv.6T [28],DF8T [21],TG8T [26],PCF10T [18], SPG11T [20],LP12T [19] SRAM cells respectively. It is attributed to the forward body bias technique in read path which reduces the threshold voltage of N5 transistor which takes minimum time to discharge the read bit-line.…”

Section: Read/write Access Timementioning

confidence: 99%

“…A data-dependent supply voltage technique in 11T SRAM cell is utilized to decreases power consumption of the cell [19]. Besides, transmission gate is used at storage node of TG8T SRAM cell as presented in Fig.2(f) to decreases write power consumption in the cell [26]. In this cell, a stacked transistor is used at a pulldown network to decrease standby power in the cell.…”

Section: Introductionmentioning

confidence: 99%

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A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

Kumar¹,

Tomar²

2021

Preprint

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This paper presents a single-ended read and differential write half select free 9T static random access memory (SRAM) cell operates in the sub-threshold region. Proposed 9T SRAM cell shows a reasonable reduction in read and write power dissipation by a factor of 1.41× and 2.1× respectively as of conventional 6T (Conv.6T) SRAM cell. The stacking of transistors at core latch network minimizes the leakage power of the cell. The read static noise margin (RSNM) and write margin (WM) are upgraded by 2.16× and 2.06× respectively as of Conv.6T cell. A forward body bias technique is utilized in read path which results to decreases in read access time by a factor of 2.72× as of standard 6T SRAM cell. The mean value of Ion/Ioff ratio of the proposed cell is improved by 2.92× as compared to the Conv.6T SRAM cell. It is attributed to a reduction in bit-line leakage current. To achieve more soundness in characteristics of the proposed 9T SRAM cell, process variation effect on RSNM, power dissipation, and read current is calculated through Monte Carlo (MC) simulation at 5000 points. The obtained results are compared with reference SRAM cells at 0.3V supply voltage.

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