2021
DOI: 10.1504/ijsse.2021.121462
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Design of energy and EDP efficient 1-bit full subtractor based divider circuits for computing systems

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Cited by 6 publications
(2 citation statements)
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“…While LSs that utilize CC techniques (Figure 2) have less standby power consumption, they are limited by a trade-off between their pull-up and pull-down networks, which affects their speed and energy consumption during switching. LSs face a challenge when up-converting sub-threshold voltages, as it causes the pull-down network areas to be too large and complex in practice [10][11][12][13]. Current-mirror-based architectures [7,10,14] perform better when a wide range of up-conversion is required, as they face more contention among pull-up and pull-down networks, which results in increased speed and reduced energy consumption.…”
Section: Introductionmentioning
confidence: 99%
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“…While LSs that utilize CC techniques (Figure 2) have less standby power consumption, they are limited by a trade-off between their pull-up and pull-down networks, which affects their speed and energy consumption during switching. LSs face a challenge when up-converting sub-threshold voltages, as it causes the pull-down network areas to be too large and complex in practice [10][11][12][13]. Current-mirror-based architectures [7,10,14] perform better when a wide range of up-conversion is required, as they face more contention among pull-up and pull-down networks, which results in increased speed and reduced energy consumption.…”
Section: Introductionmentioning
confidence: 99%
“…While LSs that utilize CC techniques (Figure 2) have less standby power consumption, they are limited by a trade-off between their pull-up and pull-down networks, which affects their speed and energy consumption during switching. LSs face a challenge when up-converting subthreshold voltages, as it causes the pull-down network areas to be too large and complex in practice [10][11][12][13].…”
Section: Introductionmentioning
confidence: 99%