Design of energy-efficient full subtractor circuit at near threshold computing for signal processing application

Abstract

Energy Efficiency is of critical significance when designing integrated circuits. In the world of advanced integrated circuits (ICs) that operate in near-threshold voltage (NTV) is gaining much awareness because of its potential for high-performance and energy-efficient designs. But, the unique problems presented by near-threshold voltage process require meticulous analysis and development of basic arithmetic circuits that minimize the impact of the process's variations as well as fluctuations in supply voltage and additional performance limitations. In this brief, a 1-bit full subtractor (FS) cell is proposed for lower power application by employing Gate Level Body Biasing (GLBB) scheme for near threshold computing (NTC) application to conquer a unique module for achieving full swing borrow output. The proposed cell offers advantages by providing high-driving capacity for both difference and borrows outputs when integrated in multistage structures such as dividers, multipliers and compressors. Power, Delay, Energy and the product of Energy with Delay (EDP) metrics were evaluated, with comparison to C-CMOS full subtractor. The proposed feedback based with FS with GLBB technique has a entire die area of 60.02 μm2, while the power (average), delay, and energy are 1138 pW, 242 ns, and 27.53 aJ, respectively. GLBB circuits achieve performance levels that are not affordable in conventional CMOS as well as DTMOS configurations. The outcomes demonstrate how efficient the FS cell can serve as an arithmetic circuit for unconventional signal processing computing applications in integrated circuits (ICs).