Design of Energy-Efficient High-Speed Links via Forward Error Correction

Abstract

In this brief, we show that forward error correction (FEC) can reduce power in high-speed serial links. This is achieved by trading off the FEC coding gain with specifications on transmit swing, analog-to-digital converter (ADC) precision, jitter tolerance, receive amplification, and by enabling higher signal constellations. For a 20-in FR4 link carrying 10-Gb/s data, we demonstrate: 1) an 18-mW/Gb/s savings in the ADC; 2) a 1-mW/Gb/s reduction in transmit driver power; 3) up to 6× improvement in transmit jitter tolerance; and 4) a 25-to 40-mV improvement in comparator offset tolerance with 3× smaller swing.

FEC-based 4 Gb/s backplane transceiver in 90nm CMOS

“…The measurement results provide a quantitative assessment of how coding gain affects the trade-off between transmit swing, jitter tolerance, BER and power. We show that much of the promise of FEC identified in [4,5] can indeed be fulfilled in practice.…”

“…A low-power decoder is implemented on the receive side. The decoder architecture [5] is shown in Fig. 6, where a simple error detector unit, similar to the encoder, gates the high-powered error correction unit.…”

“…We previously studied the application of FEC to 10 Gb/s signaling over channels with 12 to 15 dB loss at Nyquist via analysis and simulations, and concluded that binary BCH codes along with receive equalization provides a coding gain of 3 to 6 dB at a BER of 10 -15 [4,5]. The reduced SNR requirements represented by the coding gain may be employed to: (a) reduce transmit swing, (b) reduce equalizer complexity, (c) enhance jitter-tolerance, and (d) improve comparator offset tolerance.…”

System-assisted analog mixed-signal design

“…For example, in links with forward error-control (FEC), the output of a equalizer for the channel impairments needs to achieve a typical bit error-rate (BER) of 10 −3 to 10 −5 , whereas the output of the FEC decoder brings the BER down to 10 −12 or smaller. This orders-of-magnitude discrepancy in the BER specifications between the equalizer and decoder has only recently been exploited [9] to reduce power in heavily powerconstrained links such as back-plane. In this paper, we will focus on ADCs, as these are among the more power hungry blocks in high-speed links.…”

The impact of error control on energy-efficient reliable data transfers over optical networks

“…Nonetheless, many of these models cannot be directly applied to core optical networks because of the characteristics that are unique to the optical transmission medium, such as long transmission reach of the optical fiber (hundreds of kms), and high bit-rates (Gbps to Tbps). In [7] and [8], the energy efficiency of FEC devices used in optical networks was studied, but the trade-offs between FEC and transport energy were not discussed. The energy efficiency of a bufferless core optical network (enabled using a packet-level FEC scheme) was compared against a core network with large buffers in [9].…”