Design of Experiments Approach to Evaluating the Reliability of System-in-Package Assemblies

Abstract

Reliability in microelectronic packaging has been, and will continue to be, a major concern that must be taken into account early in the design of a package. System-in-package (SiP) assemblies, as well as other high density packaging technologies, are being used in many system architectures in order to incorporate a high level of integration, reduce cost and fit on tighter next higher assembly (NHA) grid spacing. While these technologies are being adopted into system architectures, there is limited test data on the reliability of these packages in military applications. A better understanding of the impacts of design variables in a SiP assembly allows the design community to determine the most appropriate packaging solution for use in a given application. The term “system-in-package” covers a wide range of microelectronic packaging technologies. Microelectronic packaging technology is trending towards taking the SiP concept and incorporating a very high level of integration within as small of a footprint as possible. In many cases, a fan out design technique is used in order to utilize die with high density bump patterns and then use an interposer technology to increase the bump pitch to match pitches achievable on NHA board technologies. While increasing the packaging density appears beneficial in theory, its reliability becomes a risk as the complexity of the assembly increases and more interfaces are added. Mechanical and structural considerations must be taken into account when designing this type of assembly in order to limit the stresses observed in the assembly, especially when exposed to environmental conditions. This study will focus on traditional two dimensional (2D) integrated circuit (IC) designs. For the purposes of this study, a 2D IC package will be considered as multiple die attached to a SiP substrate via flip-chip bumps. These SiP assemblies will in turn be attached to a test circuit board via solder bumps, which are at a larger pitch relative to the flip-chip bump patterns. A daisy-chain circuit design was incorporated into the test board and die in order to evaluate the reliability of the assembly interconnects at various points throughout the assembly. Design variables such as underfill material, SiP substrate material and flip-chip bump density were incorporated into a design of experiments in order to evaluate their impact on the reliability of a SiP assembly. The materials selected for use in this testing allow for the evaluation of the impacts of coefficient of thermal expansion (CTE), modulus and other material properties on the reliability of a SiP assembly. Reliability of the assemblies was tested via temperature cycling and biased humidity testing. Successful reliability of each test was dictated by the continuity of the daisy chain circuits throughout testing, as well as a visual examination of the interconnects after test. Samples of each assembly design configuration were used in cross sectional analysis to further examine the effects of the reliability on the assembly. Material characterization techniques such as scanning electron microscopy (SEM) and focus ion beam scanning electron microscopy (FIB-SEM) were used, as necessary, to investigate failure modes. This paper will review a design of experiments study of SiP assemblies and present the results of reliability testing on various SiP assembly designs. Further study is suggested for the use of these results in developing and refining finite element models capable of accurately predicting failure modes in SiP assemblies.