Design of Fault Tolerant Full Adder and Full Subtractor

Abstract

Now days, the complexity of integrated circuits is increasing while reliability of the components is decreasing due to small gates and transistor. One of the impacts of technology scaling is more sensitivity to transient and permanent faults. So, fault tolerant system plays important role in critical application where immediate human action is not possible. For reliable and efficient operation of a system, the detection of the transient fault is necessary. It is very difficult to detect these faults offline. The fault tolerant circuits can detect the faults and tolerate the detected faults. There are many fault tolerant full adder and full subtractor which can detect these faults online. So, an efficient fault tolerant design is proposed for full adder and full subtractor in this paper which can detect the faults with their exact location and also tolerate the faults. The proposed designs can detect the faults in single and multi net. The design has less area overhead and has less power requirements as compared to the previous techniques.