2016 Power Systems Computation Conference (PSCC) 2016
DOI: 10.1109/pscc.2016.7541021
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Design of ferroresonance suppression circuit for capacitive voltage transformer - analytical approach supported by simulation

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Cited by 4 publications
(2 citation statements)
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“…Owing to the low‐pass filtering feature of CVT, some of the fault‐generated transients in voltage signals are filtered out. To analyse this effect on the proposed method, the voltage signals are recorded after stepping down by a CVT, in which a 21 kV/110 V voltage transformer is modelled with the non‐linear magnetising core characteristics and active ferroresonance suppression circuit as provided in [28]. Incorporating this CVT in the WSCC system, the same fault as represented in Fig.…”
Section: Resultsmentioning
confidence: 99%
“…Owing to the low‐pass filtering feature of CVT, some of the fault‐generated transients in voltage signals are filtered out. To analyse this effect on the proposed method, the voltage signals are recorded after stepping down by a CVT, in which a 21 kV/110 V voltage transformer is modelled with the non‐linear magnetising core characteristics and active ferroresonance suppression circuit as provided in [28]. Incorporating this CVT in the WSCC system, the same fault as represented in Fig.…”
Section: Resultsmentioning
confidence: 99%
“…Abbasi et al [40] introduced ferroresonance limiter consists of damping resistor resulted in eliminate of chaotic ferroresonance oscillations started with series capacitors controlled by thyristor in the CVT. Izykowski et al [41] introduced the design of two ferroresonance suppression circuit implemented on the step down side of the CVT. The first is to use a resistance only, and the second is to use RLC circuit.…”
Section: Ferroresonance Mitigationmentioning
confidence: 99%