Design of Flexible Multiplier Using Wallace Tree Structure for ECC Processor Over Galosis Field

Lakshmi, C.; Jayarin, P. Jesu

doi:10.1007/978-3-030-32150-5_77

Cited by 1 publication

(1 citation statement)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Here, we concentrate on arithmetic unit, because, it consumes more hardware than other units. The proposed multiplier is shown in figure 3 uses two high speed adders such as MBM and Wallace tree multiplier which are hybridized with CLA to perform the final accumulation of the partial products [35]. The multiplication process consists of three steps.…”

Section: Data Encapsulation Using Ecc Processormentioning

confidence: 99%

Reconfigurable Design of Low Power Hybrid Crypto Processor using Signcryption for Wireless Networks

Lakshmi¹

2020

IJATCSE

View full text Add to dashboard Cite

Now a day all the communications are carried out in wireless medium. It is necessary to transmit the confidential data in wireless media in secure manner. Cryptography is technique to protect electronic data in communication network. Hardware implementation of cryptography processor in field programmable gate array (FPGA) is major issues in terms of area, power and throughput. In this paper, we propose a hybrid crypto processor (HCP) for wireless network using flexible encryption and signature techniques. The main aim of proposed HCP technique used to provides secure wireless communication with aware of malicious attacks in the network, know to my knowledge, the proposed HCP hardware design is open the platform in signcryption. Generally, hybrid cryptography consists of data encapsulation mechanism (DEM) and key encapsulation mechanism (KEM). In HCP design, the efficient multiplier based ECC processor is proposed for data encapsulation over Galois field (GF (2 m )). Moreover, the improved enhanced Kurosawa and Desmedt hashing (EKD) hashing scheme is proposed for key encapsulation. The proposed HCP design is implementing in Xilinx tool with different field programmable gate array (FPGA) families. The result shows that effectiveness of proposed HCP design in terms of hardware utilization, power consumption and throughput over existing design.

show abstract

Section: Data Encapsulation Using Ecc Processormentioning

confidence: 99%

Reconfigurable Design of Low Power Hybrid Crypto Processor using Signcryption for Wireless Networks

Lakshmi¹

2020

IJATCSE

View full text Add to dashboard Cite

show abstract

Design of Flexible Multiplier Using Wallace Tree Structure for ECC Processor Over Galosis Field

Cited by 1 publication

References 14 publications

Reconfigurable Design of Low Power Hybrid Crypto Processor using Signcryption for Wireless Networks

Reconfigurable Design of Low Power Hybrid Crypto Processor using Signcryption for Wireless Networks

Contact Info

Product

Resources

About