Design of high-K dielectric HSS-DMG Junctionless FinFET using hetero GOS for nanoscale application

Abstract

This article presents a detailed investigation of the High-K dielectric horizontal stack spacer (HSS) dual material gate junction-less FinFET device for analog and RF application using the gate oxide stack (GOS) approach. At first, the impact of the horizontal stack spacer (HSS) with different high-K spacer materials are investigated by placing different dielectric material like HfO2, SiO2, Si3N4, and TiO2 on the horizontal spacer. The simulation results of the device indicate that the High-K dielectric HSS makes the device high stability toward the leakage current and static power dissipation at the sub-nano scale regime. The DC characteristics of the device are also investigated alongside the AC/RF characteristics. The proposed device predominantly improves performance in terms of parameters like subthreshold swing, Ion/Ioff, and DIBL. The proposed device shows a high ON current of 8.56×10 -5(A), which is about 15% higher than the existing literature, and the device also makes a notable impact on the leakage current by restricting it to 9.635×10-12. The simulation of the device is carried out with optimization of the doping to investigate and improve the device's performance. The device shows an excellent improvement in performance which is highly suitable for future-ready device applications.