2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03 2003
DOI: 10.1109/icasic.2003.1277613
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Design of high performance CMOS current-mode winner-take-all circuit

Chien-Cheng Yu1,
Yun-Ching Tang Yun-Ching Tang2,
Bin-Da Liu Bin-Da Liu3
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Cited by 4 publications
(1 citation statement)
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“…Figure 17. Power-Speed diagram of prior WTA/LTA circuits depending on the architecture[8,10,16,18,20,22,30,36,39,43].…”
mentioning
confidence: 99%

Winner-Take-All and Loser-Take-All Circuits: Architectures, Applications and Analytical Comparison

Rahiminejad,
Aminzadeh
2023
Chips
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0
0
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“…Figure 17. Power-Speed diagram of prior WTA/LTA circuits depending on the architecture[8,10,16,18,20,22,30,36,39,43].…”
mentioning
confidence: 99%

Winner-Take-All and Loser-Take-All Circuits: Architectures, Applications and Analytical Comparison

Rahiminejad,
Aminzadeh
2023
Chips
1
0
0
0
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Low power current-mode binary-tree asynchronous Min/Max circuit

Długosz
1
,
Talaka
2
2010
Microelectronics Journal
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High-Precision Current-Based CMOS WTA/LTA Filters

Sánchez-Gaspariano
1
,
Dlaz-Sanchez
2
,
Saldana-Gonzalez
3
2007
17th International Conference on Electronics, Communications and Computers (CONIELECOMP'07)
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