Design of High-Performance Full Adder Using 20nm CNTFET Technology

Naveen, G.; Rao, V.R Seshagiri; Nirmala., N; L, Pavan Kalyan.; Vijay, Vallabhuni; Venkateswarlu, S. China; Vallabhuni, Rajeev Ratna

doi:10.1109/icrtcst54752.2022.9782042

Cited by 12 publications

(13 citation statements)

References 12 publications

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“…Due to their higher threshold voltage, previously known methods cannot be operated at low voltages. [32][33][34][35][36][37][38][39] This tells us that the previously known and current known methodologies had a significant drawback which creates the need to invent new methodologies to make the circuit more efficient. It is also known that the static leakage current is also more in existing and previously known methodologies.…”

Section: Significant Drawbacks In the Existed Methodsmentioning

confidence: 99%

ADC: Novel Methodology for Code Converter Application for Data Processing

2023

VLSI

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An innovative "Multiplexer based Thermometer to Binary code encoder" is presented in this paper. This paper shows a relative decrease in the total count of multiplexers used which eventually reduces the no of transistors used when compared to traditional Architectures. The requirement for further more inverters is also eliminated in the proposed model. The input thermometer code is at first is converted to the respective gray code with the help of 2:1 multiplexer. Thereafter, using two-input XOR gates the conversion process of gray code to respective binary codes takes place. Outcomes of simulation reveal that there is an approximately 80% decrease in the power consumption which is a great reduction actually when differentiated with previously known and current encoder architectures with the delay being reduced from 0.472ps to 0.366 ps. This throws a light on modern power-saving encoder architectures and has a greater significance in the future. The proposed encoder gives a better application for future generation advanced ADC & related circuits.

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Section: Significant Drawbacks In the Existed Methodsmentioning

confidence: 99%

ADC: Novel Methodology for Code Converter Application for Data Processing

2023

VLSI

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“…[15][16][17][18][19][20][21][22][23][24][25] The 32-bit comparator is designed and implemented using Cadence virtuoso tool at 180 nm technology and is compared with the Raman's Full adder based 32-bit comparator architecture. [7] The Proposed architecture of Full adder based 32-bit comparator is as shown in the Fig. 1.…”

Section: Existing Comparatorsmentioning

confidence: 99%

Data Distinguisher Module Implementation using CMOS Techniques

2023

VLSI

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Comparator plays a vital role in many IC applications, Microprocessors, computer systems etc. Hence it is desirable to design a comparator block with low power consumption and high speed performance .In this paper a novel architecture of 32-bit comparator using Complementary metal-oxide semiconductor logic is proposed and computed its delay and power metrics. Further it is compared with the full adder based 32-bit comparator. From the analysis we derive the comparison between proposed and the conventional comparator. The complete designing of architectures and their result analysis was done in cadence virtuoso tool at 180 nm technology. Simulation results show that there is reduce in power consumption of 90% when compared to the conventional full adder based comparator.

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“…Therefore, the power dissipation can have a significant effect on the performance of the memory design. [6][7][8][9][10][11] The parameters such as SNM, power, read and write are needed to be considered for planning of SRAM. Some methods might not guarantee the thermal stability of the memory system, thus a unifying framework for analysis and magnificence of 8T and 10T cell design for SRAM is to be considered.…”

Section: Introductionmentioning

confidence: 99%

Flip-Flop Realization: Conventional Memory Elements Design with Transistor Nodes

2023

VLSI

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In the ultra-low-power implementation, center circuits of numerous frameworks are activated by inadequate occasions, for example, the Internet of Things (IoT) sensors and implantable clinical consideration. To guarantee that, the sensors get each and every occasion showing up whenever the circuits operate in standby mode the most of the time. Under such conditions, static power dominates in the total power consumption. For these implementations, the lessening framework leakage current can straightforwardly accomplish the greatest effectiveness of the complete framework power utilization. Since the SRAM cluster takes up a bigger bit of the circuit, it is important to decrease the power utilization of the SRAM exhibit so as to lessen circuit all-out power. Band-to-band tunneling (BTBT) mechanism introduced silicon tunnel FET (TFET), MOSFET compatible fabrication process and ultra-steep SS, which can break the 60mV/dec limitation of MOSFET at room temperature and ultralow off-state current. Subsequently, it is required to be a promising contender for an ultra-low-power rationale circuit. The impact of forward p-I-n leakage current could prompt harm to the static noise margin (SNM), static power and power defer result of the SRAM circuit. So the proposed topology can stay away from the p-I-n intersection, by expanding SRAM cell read and hold static noise margin (SNM) and diminishing static power utilization drastically.

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Design of High-Performance Full Adder Using 20nm CNTFET Technology

Cited by 12 publications

References 12 publications

ADC: Novel Methodology for Code Converter Application for Data Processing

ADC: Novel Methodology for Code Converter Application for Data Processing

Data Distinguisher Module Implementation using CMOS Techniques

Flip-Flop Realization: Conventional Memory Elements Design with Transistor Nodes

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