Design of high PSRR folded cascode operational amplifier for LDO applications

Gupta, Harsh K.; Mishra, Gaurav Kumar; Rizvi, Navaid Zafar; Patnaik, Santosh K.

doi:10.1109/iceeot.2016.7755591

Cited by 11 publications

(3 citation statements)

References 3 publications

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“…Furthermore, the comparisons of the performance specifications of the very LVs CMOS GD Op-Amp circuit with the other Op-Amp circuits presented in the prior papers [11,23,25] are summarized in Table 4. It is evident from Table 4 that the very LVs CMOS GD Op-Amp circuit presented in this paper has better performance specifications values in terms of the overall gain ( ), unity gain bandwidth (GBW), output voltage swing which is approximately rail-to-rail swing, equivalent input-referred noise (IRN) voltage, settling time ( ), input common-mode range (ICMR) voltage, and power-supply rejection ratios ( ), whereas its main drawback is it has a higher total power dissipation ( ) value.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…MOSFETs circuits, and the only solution to keep pace with the performance of the digital MOSFETs circuits is to choose suitable and simple analog MOSFETs circuits topologies with very LVs power supplies. CMOS operational amplifier (Op-Amp) circuits with different topologies are the main building blocks that perform useful and multiple functions in the analog and mixed-signal integrated circuits (ICs) [10][11][12][13]. Consequently, the selection of suitable and simple design for very LVs power supplies and high-performance specifications CMOS Op-Amp circuits is very crucial because their performance specifications directly affect the overall performance specifications of the analog and mixed-signal ICs.…”

Section: Introductionmentioning

confidence: 99%

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Design of very low-voltages and high-performance CMOS gate-driven operational amplifier

AL-Qaysi

Jasim

Hameed

2020

IJEECS

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This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design of very low-voltages and high-performance CMOS gate-driven operational amplifier

AL-Qaysi

Jasim

Hameed

2020

IJEECS

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“…Iot devices and wearable electronics require lower standby power consumption and power supply noise. The LDO is required to have extremely high power ripple suppression [2] . So it is of practical significance and demand to design a LDO circuit with low quiescent current and high power supply rejection ratio.…”

Section: Introductionmentioning

confidence: 99%

A low quiescent current high PSRR LDO circuit

Zhou,

Zhu,

Lin

et al. 2024

Third International Conference on Computer Technology, Information Engineering, and Electron Materials (CTIEEM 2023)

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In order to meet the needs of Internet of Things devices and wearable electronic devices for lower standby power consumption and power supply noise, a Low Dropout Regulator (LDO) circuit with low quiescent current and high power supply rejection ratio is designed. The core circuit is bandgap and error amplifier. This design is based on the 0.18um BCD process. The Spectre simulation of Cadence has been used to test and simulate the circuit. The simulation result indicates that the bandgap voltage is 1.209V, the temperature coefficient is 19.76ppm/°C in the range of -25~125°C, and the power supply rejection ratio is 69dB at low frequency. The circuit can deliver a quiescent current of around 776nA and exhibits good temperature characteristics and low quiescent current.

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