Design of high-speed low-power 3-2 counter and 4-2compressor for fast multipliers

Hsiao, Shen-Fu; Jiang, Ming-Roun; Yeh, J. S.

doi:10.1049/el:19980306

Cited by 101 publications

(43 citation statements)

References 2 publications

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“…We have used 3-2 (Hsiao et al, 1998) and 4-2 compressors of (Chang et al, 2004;Ng and Lau, 1999;Prasad and Parhi, 2001;Baran et al, 2010;Ma and Li, 2008) in our 8 bit, 16 bit and 24 bit multipliers and found that our proposed higher order compressors give higher speed and lesser area Table 2. Figure 6-8 respectively shows the speed, area and power comparison of a multiplier using both low and high order compressors.…”

Section: Multiplier Performance and Comparisonmentioning

confidence: 99%

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Design of 8-4 and 9-4 Compressors Forhigh Speed Multiplication

Marimuthu¹

2013

American Journal of Applied Sciences

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This study presents higher order compressors which can be effectively used for high speed multiplications. The proposed compressors offer less delay and area. But the Energy Delay Product (EDP) is slightly higher than lower order compressors. The performance of 8×8, 16×16 and 24×24 multipliers using the proposed higher order compressors has been compared with the same multipliers using lower order compressors and found that the new structures can be used for high speed multiplications. These compressors are simulated with Cadence RTL complier at a temperature of 25°C with the supply voltage of 1.2 V.

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Section: Multiplier Performance and Comparisonmentioning

confidence: 99%

“…Various approaches have been proposed to improve their speed. As for example, 4-2 compressors were implemented with 3 XOR delays (Hsiao et al, 1998;Gu and Chang, 2003;Chang et al, 2004;Ma and Li, 2008). …”

Section: Introductionmentioning

confidence: 99%

Design of 8-4 and 9-4 Compressors Forhigh Speed Multiplication

Marimuthu¹

2013

American Journal of Applied Sciences

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“…The use of 4:2 compressors decrease the wiring capacitance due to a more regular layout, thereby contributing to fewer transitions in the reduction tree which results in reduced power. Hsiao et al (1998) proposed a modified design of the 4:2 compressor that claimed improvements in both delay and power dissipation compared to earlier designs (Hsiao et al, 1998). Several logic and circuit level optimizations are possible for reducing the number of transitions in the partial product reduction stage using higher order compressors instead of simple FA cells and 4:2 compressors.…”

Section: Related Researchmentioning

confidence: 99%

Low Power Multiplier by Effective Capacitance Reduction

Peddamgari¹,

Radhakrishnan²

2017

American Journal of Engineering and Applied Sciences

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In this study we present an energy efficient multiplier design based on effective capacitance minimization. Only the partial product reduction stage in the multiplier is considered in this research. The effective capacitance at a node is defined as the product of capacitance and switching activity at that node. Hence to minimize the effective capacitance, we decided to ensure that the switching activity of nodes with higher capacitance is kept to a minimum. This is achieved by wiring the higher switching activity signals to nodes with lower capacitance and vice versa, for the 4:2 compressor and adder cells. This reduced the overall switching capacitance, thereby reducing the total power consumption of the multiplier. Power analysis was done by synthesizing our design on Spartan-3E FPGA. The dynamic power for our 16×16 multiplier was measured as 360.74 mW and the total power 443.31 mW. This is 17.4% less compared to the most recent design. Also, we noticed that our design has the lowest power-delay product compared to the multipliers presented in literature.

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“…A 3-2 compressor takes 3 inputs X1, X2, X3 and generates 2 outputs, the sum bit 's', and the carry bit 'c' as shown in Figure 3 [11]. In this A+B+C+D= (A+B) + (C+D).…”

Section: Figure 3: a 3:2 Compressormentioning

confidence: 99%

Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA

Kaur¹,

Patial²

2013

IJCA

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This paper presents 16×16 bit Radix-4 Modified Booth's Multiplier (MBM) optimized for high speed multiplication by using pipeline Technique. This paper aims at reduction of hardware utilization. This is accomplished by the use of 3:2 compressor adders. An efficient VHDL code has been written, successfully simulated on Modelsim 10.2 simulator and Xilinx 12.4 navigator is used for synthesizing the code. Simulation result shows the clock period of 2.689ns. The selected device to synthesize the code is xc3s500e-4pq208 of Sartan-3E family. The area utilization is shown as 222 numbers of slices and 383 numbers of LUTs. General Terms: Multiplier, Pipelining Technique

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Design of high-speed low-power 3-2 counter and 4-2compressor for fast multipliers

Cited by 101 publications

References 2 publications

Design of 8-4 and 9-4 Compressors Forhigh Speed Multiplication

Design of 8-4 and 9-4 Compressors Forhigh Speed Multiplication

Low Power Multiplier by Effective Capacitance Reduction

Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA

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