Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

Elangovan, M.; Abbasian, Erfan; Gunasegeran, Muthukumaran; Sofimowloodi, Sobhan

doi:10.1016/j.aeue.2022.154308

Cited by 28 publications

(15 citation statements)

References 28 publications

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“…17 A CNT shows either metallic or semiconducting properties based on the chirality vector (n, m), where both n and m are integers. 5 For n = m or n-m = 3i, where i is an integer, a CNT is metallic, and otherwise, it is semiconducting. 4 The CNT diameter (D CNT ) is calculated by Eq.…”

Section: Carbon Nanotube Field-effect Transistor (Cntfet)mentioning

confidence: 99%

“…4 Moreover, CNTFET has high mobility, high ON-to-OFF currents ratio (I ON /I OFF ), and good transconductance, consumes low power, and mitigates parametric variations. 5 Due to these reasons, CNTFET is the best candidate to design power/energy-efficient digital circuits. 4 To further improve the power/energy efficiency in a digital circuit, the use of multiple-valued logic (MVL) is the best way because it uses more than two logical values for computations compared to binary logic.…”

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confidence: 99%

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A High-Speed Low-Energy One-Trit Ternary Multiplier Circuit Design in CNTFET Technology

Abbasian¹,

Nayeri²

2023

ECS J. Solid State Sci. Technol.

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Contemporary system-on-chip-based applications are battery-powered. To increase the operation time, they need various low-power/energy circuits. Carbon nanotube field-effect transistor (CNTFET) is a potential alternative to complementary metal-oxide-semiconductor for power/energy-efficient circuits implementation due to its high performance. Another way to reduce power/energy consumption in a circuit is to use multiple-valued logic, especially ternary logic, which has three logical states. This paper presents a novel 1-trit ternary multiplier circuit with 23 transistors based on only unary operators of the ternary logic system and the dual-supply voltages technique. The proposed design does not use the ternary decoder/encoder, logic gates, cascading transmission gates, and ternary multiplexer to reduce the transistors count, delay, power, and energy. The Stanford CNTFET model in the 32-nm technology node is used to simulate the proposed design. The delay, power, and delay-power-product (PDP) of the proposed design at 0.9V are 0.026ns, 0.139μW, and 3.614aJ, respectively. It offers improvements between 50% and 61.19% in delay and between 52.72% and 59.75% in PDP compared to previously published multiplier circuits, which are based on the dual-supply voltages and use 23 transistors. These improvements make the proposed design a good candidate for the design of the next generation of multiplier circuits in arithmetic blocks.

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Section: Carbon Nanotube Field-effect Transistor (Cntfet)mentioning

confidence: 99%

mentioning

confidence: 99%

A High-Speed Low-Energy One-Trit Ternary Multiplier Circuit Design in CNTFET Technology

Abbasian¹,

Nayeri²

2023

ECS J. Solid State Sci. Technol.

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“…So, there is a need to look for different potential alternatives to CMOS. It is found that carbon nanotube field‐effect transistors (CNTFET) and graphene nanoribbon field‐effect transistors (GNRFET) have a higher power of switch, curves with more ideal voltage, and better mobility, consequently, they can be favorable replacements for CMOS 11–14 …”

Section: Introductionmentioning

confidence: 99%

“…It is found that carbon nanotube field-effect transistors (CNTFET) and graphene nanoribbon field-effect transistors (GNRFET) have a higher power of switch, curves with more ideal voltage, and better mobility, consequently, they can be favorable replacements for CMOS. [11][12][13][14] GNRFET, unlike CNTFET, is compatible with the existing CMOS manufacturing technologies. CNTFET has alignment and transfer-related issues, which can be resolved by GNRFET.…”

mentioning

confidence: 99%

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

Abbasian,

Orouji,

Taghipour Anvari

et al. 2023

Circuit Theory & Apps

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SummaryInternet‐of‐Things (IoTs)‐based embedded systems require energy‐efficient designs for long‐term operation. To achieve energy‐efficient designs, multiple‐valued logic (MVL) circuits and graphene nanoribbon field‐effect transistors (GNRFETs) are used instead of binary logic circuits and complementary metal‐oxide‐semiconductor (CMOS), respectively. This paper presents a novel ultra‐low power and energy‐efficient ternary Half‐Adder (THA) circuit based on unary operators, two power supplies (dual‐VDD), VDD and VDD/2, and two ternary 3:1 multiplexers in 32 nm GNRFET technology. The superiority of the proposed design are improvements between 2.86% and 60% in transistor count, between 86.12% and 97.15% in power consumption, and between 58.14% and 98.39% in power‐delay‐product (PDP) compared to existing THA circuits. Moreover, the proposed THA circuit is also implemented with 32 nm carbon nanotube field‐effect transistors (CNTFETs). Simulation results indicate that the proposed GNRFET‐based THA circuit increases delay by 1.74 × and reduces power/PDP by 89.41%/81.63% compared to its CNTFET‐based counterpart.

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“…[4][5][6][7] These problems reduce the suitability of the MOSFET for power/energy-efficient applications. 5 In response, researchers have proposed various new alternative solutions and technologies to traditional MOSFET technology, such as fin-based FET (FinFET), [8][9][10][11][12][13][14] carbon nanotube-based FET (CNTFET), 6,7,15,16 and graphene nanoribbon-based FET (GNRFET). 4,[17][18][19] Among these emerging technologies, GNRFET offers excellent properties and is compatible with existing silicon-based MOSFET, and is an attractive option for achieving higher performance and efficiency in future electronic devices.…”

mentioning

confidence: 99%

A Power Efficient 32 nm Ternary Multiplier using Graphene Nanoribbon Field-Effect Transistor Technology

Rohani,

Emrani Zarandi

2023

ECS J. Solid State Sci. Technol.

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To address interconnections and energy issues associated with binary logic, designers are increasingly turning to ternary logic. One effective approach to implementing ternary logic-based circuits is to use a multiple-threshold voltage (multi-Vth) design. In particular, graphene nanoribbon (GNR)-based field-effect transistors (GNRFETs) are a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology for sub-32nm feature sizes, as GNRs have excellent properties that can overcome scaling issues in CMOS. This paper introduces a ternary multiplier implemented with 32 nm GNRFET technology, which demonstrates high efficiency with only 26 transistors. Simulation results show that the proposed multiplier improves power dissipation and product-delay-power (PDP) by at least 37.30% and 22.22%, respectively, compared to existing multiplier designs when run at 0.9V. Moreover, our proposed design is implemented with a carbon nanotube-based FET (CNTFET) technology. The GNRFET-based multiplier improved power and PDP by 41.77% and 30%, respectively in the cost of increasing the delay by 25%, compared to its CNTFET-based equivalent. Finally, we analyze the proposed multiplier under the process and environmental parameters variations of GNRFET technology. Overall, our results demonstrate the advantages of using GNRFET technology for implementing ternary logic-based circuits and provide insight into the impact of different design choices on performance.

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Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

Cited by 28 publications

References 28 publications

A High-Speed Low-Energy One-Trit Ternary Multiplier Circuit Design in CNTFET Technology

A High-Speed Low-Energy One-Trit Ternary Multiplier Circuit Design in CNTFET Technology

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

A Power Efficient 32 nm Ternary Multiplier using Graphene Nanoribbon Field-Effect Transistor Technology

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