Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter

Abstract

This work presents three different approaches which eliminates the resistor ladder completely and hencereduce the power demand drastically of a Analog to Digital Converter. The first approach is SwitchedInverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches areclocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in powerdissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SISADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC