Design of Low Power and Secure Implementation of SBox and Inverse-SBox for AES

Due to advent in CMOS technology, it has become possible now to put millions of transistors on a single chip of silicon. This has drastically increased the performance of the device and it can do much faster operations. But on the other side, putting more transistors on a silicon chip triggering the problem of increased power consumption. So, it becomes a bottleneck for the designer to choose in between performance and power consumption. Particularly, for reconfigurable hardware like FPGAs the situation is worst and demands concern. So, this paper presents some optimization techniques that are applied on FPGAs at different levels of abstraction. Some benchmark circuits like ALU, Register, Counter and RAM are used for experimental measurements to validate the results. After simulation and power analysis of benchmark circuits at different frequencies, a power aware utility software is developed that performs optimization of power keeping performance in consideration at a given frequency for the selected FPGA. The circuits have been implemented using VHDL as the hardware description language and simulation is carried out using Xilinx ISE 14.1 by targeting Virtex-4, 5 and Artix-7 FPGA.

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Design of Low Power and Secure Implementation of SBox and Inverse-SBox for AES

Abstract: In the cutting edge world, data security has turned into an essential issue furthermore the innovation is going to increment quickly. In this paper, the symmetric key standard for encryption and decoding is propelled Encryption standard (AES) Xilinx ISE 14.1i and ModelSim 6.0.

Cited by 2 publications

References 2 publications

CMOS operational amplifier design for industrial and biopotential applications: Comprehensive review and circuit implementation

CMOS operational amplifier design for industrial and biopotential applications: Comprehensive review and circuit implementation

Matlab Interface For Power And Timing Analysis Of Digital Circuits

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