Design of Low Power Full Adder Using ONOFIC Approach

Abstract

Improving performance with reduced power consumption and chip area are the main constraint for designing VLSI CMOS circuits. The high performance low power ONOFIC approach for VLSI CMOS circuits reduces the power dissipation and improves the speed of a VLSI circuit design. In this paper, high performance and low power full adder based on ONOFIC approach have been implemented. The proposed method reduces the power dissipation and improves the speed of full adder circuit . The On/Off logic (ONOFIC) approach reduces the leakage current and leakage power with simple and single threshold voltage circuit level approach. This approach efficiently reduces the leakage current in both active and standby mode of logic circuit. The tool used for implementing the design is EDA TANNER 13.0 tool. The ONOFIC approach results have been compared with LECTOR technique and observed that the ONOFIC approach shows the improved performance and reduced power dissipation. Keywords: Leakage Current, ONOFIC, LECTOR, EDA TANNER 13.0. I. INTRODUCTIONPower dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. The main sources of power dissipation are: 1) Dynamic power dissipation due to the charging and discharging of the load capacitance. 2) Short-circuit current due to the existence of a conducting path between the voltage supply and ground for the brief period during which a logic gate makes a transition. 3) Leakage current. The leakage current consists of reverse-bias diode currents and sub threshold current. The former is due to the stored charge between the drain and bulk of active transistors while the latter is due to the carrier diffusion between the source and drain of the OFF transistors. Also, gate induced drain leakage and gate direct tunneling leakage have become the significant sources of leakage power. In deep submicron CMOS technologies, the role of sub threshold leakage power dissipation becomes dominant among other leakage power components. Modern portable electronic devices such as mobile phones, laptops, PDA's (personal digital assistant) etc are affected by high power consumption which reduces the battery backup time. The device density of these devices has been increased to improve the performance of the circuit. So there is a need for low power design methodology to limit the power consumption in high density VLSI chips. Voltage scaling is one of the effective techniques to reduce the power consumption in electronic devices. In electronic devices, to control the power consumption a supply voltage plays an important role. Supply voltage scaling without scaling of threshold voltage degrades the performance of the device. By reduction of threshold voltage and supply voltages proportionally retains the performance. The threshold voltage reduction leads to the five times higher leakage current. Adopting new lower level technologies leads to the increase in power dissipation in integrated circuits. A perfect designer concentrates mostly for efficient techniques for leakage current redu...