Design of Low Power Low Input Impedance CMOS Current Comparator

Abstract

This paper presents the new design of a CMOS current comparator with ultra low input impedance, which especially benefits on enhancing the accuracy of pulse-width-modulation (PWM). The proposed design reduces the input impedance by utilizing common-gate structure as input stage. A novel low power with high performance low current comparator is proposed in this paper which comprises of low input impedance using a simple biasing method. The further use of a commonsource feedback structure also enables extremely reduction of the input impedance. In addition, the proposed design can be applied to perform precise comparison between two terminals with varied currents since the input impedances are well designed to be balanced. The experiment results demonstrate competitive performance. With input current of 25MHz square wave, the input impedance and of comparator are merely 57.2ȍ while the average power consumption is about 9.08mW under the implementation of TSMC 0.35ȝm CMOS process with 3.3V power supply.

Design and Analysis of Pulse width Modulator (PWM) using Low Input Impedance Current Comparator

“…We therefore have to put them in the same well during physical level implement to reduce the mismatch between these two input stages [10]. The transient waveform of current comparator is shown in Fig 3. …”

A novel dual-modulation design low input impedance current comparator

“…< μA), the output voltage will not be recognizable as either logic 1 or 0, therefore has lower accuracy and slower speed. Other literatures focused on input impedance reduction and increasing output impedance to improve accuracy and speed of their current comparators [3][4][5]7,8]. This paper used a novel concept (dual-modulation) to increase the accuracy while still keeping the input impedance and output impedance, low and high, respectively.…”