Design of Low Power Modular (x mod p) Reduction Unit Based on Switching Activity for Data Security Applications

Pakkiraiah, C.; Satyanarayana, R.V.S.

doi:10.1007/978-981-19-6780-1_2

Cited by 1 publication

(1 citation statement)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The push was made to gate the clock signal and disable some of the clock tree distribution in order to decrease power dissipation (Gaupa & Akhter, 2022). The comprehensive overview of clock dissemination mechanisms can be found in (Pakkiraiah & Satyanarayana, 2022). While introducing clock gating can greatly increase a design's power efficiency, doing so makes it more difficult to disperse the clock signal.…”

Section: Related Workmentioning

confidence: 99%

Effects of logic glitch and (area-power dissipation) leakage on cryptosystems using clock gating technique to enhance web etiquette

Ehis¹

2023

Braz. J. of Sci.

View full text Add to dashboard Cite

The last century has seen an evolution in technology that has improved communication systems and, in general, made life easier for people. Our communication systems have become faster and more dependable as a result of the explosion of gadgets and services. But, these upgrades come at a price. The power consumption is one of the most worrying costs. In recent years, the solution involved installing larger, more powerful batteries—so long as doing so did not limit mobility. Today's economic and environmental problems compel us to consider alternative solutions, like methods for lowering the power consumption of digital devices. This study focuses on using digital circuits, which promise to deliver good energy efficiency and desirable performance at very low voltage savings. Certain digital switches are allegedly redundant and not required for the circuit to function properly, yet they continue to use energy. So, one of the primary issues for low power design is reducing such redundant switches. Subthreshold conduction in digital circuits is typically seen as a “parasitic” leakage in a condition where there should ideally be no conduction. Sub-threshold activities thereby reduce the problem of lowering power consumption, but do so at the expense of system throughput deterioration, fluctuations in system stability and functionality, temperature variations, and most critically, design space utilization. In order to minimize some of these redundant switches and to make circuits more energy-efficient while maintaining functionality, this study suggests two novel techniques. It uses an optimization method based on threshold voltage change to reduce glitch power. A glitch-free circuit netlist is created using an algorithm, while still maintaining the requisite delay performance. Using this approach results in a 6.14% overall reduction in energy consumption.

show abstract

Section: Related Workmentioning

confidence: 99%

Effects of logic glitch and (area-power dissipation) leakage on cryptosystems using clock gating technique to enhance web etiquette

Ehis¹

2023

Braz. J. of Sci.

View full text Add to dashboard Cite

show abstract

Design of Low Power Modular (x mod p) Reduction Unit Based on Switching Activity for Data Security Applications

Cited by 1 publication

References 12 publications

Effects of logic glitch and (area-power dissipation) leakage on cryptosystems using clock gating technique to enhance web etiquette

Effects of logic glitch and (area-power dissipation) leakage on cryptosystems using clock gating technique to enhance web etiquette

Contact Info

Product

Resources

About