2020
DOI: 10.1007/978-981-15-1483-8_13
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Design of Low Power Reduced Complexity Wallace Tree Multiplier Using Positive Feedback Adiabatic Logic

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Cited by 11 publications
(4 citation statements)
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“…M. G. Ganavi and B.S. Premananda [29] have proposed a Wallace tree multiplier using adiabatic logic. Here, the authors have used the positive feedback adiabatic logic in CMOS 180 nm technology.…”
Section: Related Work On Multipliers Using Qcamentioning
confidence: 99%
See 2 more Smart Citations
“…M. G. Ganavi and B.S. Premananda [29] have proposed a Wallace tree multiplier using adiabatic logic. Here, the authors have used the positive feedback adiabatic logic in CMOS 180 nm technology.…”
Section: Related Work On Multipliers Using Qcamentioning
confidence: 99%
“…12, it is clear that the power dissipation of the proposed multiplier is very less compared to the existing multipliers. Hence, the 4 × 4 multiplier, designed with proposed 1-bit full adder, dissipated only 2.44nW power, which is quite less compared to the power dissipation of the Wallace tree and Baugh-Wooley multipliers developed in [29], [41], [42] and [43] where the power dissipation is 22.62 µW, 4.11 µW, 67.38mW, 4.6 µW and 0.49 W, respectively.…”
Section: Power Analysis Of the Proposed Baugh-wooley Multipliermentioning
confidence: 99%
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“…Most portable systems consume more power due to limited battery life [15][16] [17]. Energy delivery, analog-digital conversion, signal processing, and data communication are activities that typically require biomedical electronic devices that have relatively low power consumption requirements [18] [19]. The need for compact, efficient, and frequently used devices is very high [20].…”
Section: Introductionmentioning
confidence: 99%