Design of MAC unit for digital filters in signal processing and communication

Harish, Basavoju; Rukmini, M. S. S.; Sivani, K.

doi:10.1007/s10772-021-09824-0

Cited by 8 publications

(3 citation statements)

References 22 publications

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“…where two 8bit values with a carry select adder are calculated with the aid of 2 adders. Hence, two Ripple carry adders does the reckoning twice with the presumption of the carry "0" and other would be "1" [2].…”

Section: Carry Select Addermentioning

confidence: 99%

“…As a whole, this is our expected new mac unit, as theoretically, these individual modules are compared to the generic adder and generic multiplier; expectation in terms of delay might be reduced, the mac using different modules were clubbed and formed as a mac unit for an instance we can use Ripple carry as the adder module. The Vedic multiplier or numerous multipliers can be used as the multiplier module so are the adder modules [2].…”

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of High Speed 32-bit MAC Unit

Bharghava ram dinesh,

Vinoth,

Kasyap

2023

J. Phys.: Conf. Ser.

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Due to the recent advances in VLSI technology, the need for efficient real time signal processing units have increased. The multiplier-and-accumulator (MAC) unit is the essential element of the digital signal processor. The aim is to design an 32-bit MAC unit that can perform multiplication and accumulation operation. Hence designing an effective MAC unit with reduced latency is necessary for better performance. The proposed MAC unit uses Carry-Select adder and Vedic multiplier which offers better speed (1.746 ns) in comparison with MAC unit designed using Ripple carry adder (1.782 ns). Urdhva tiryaghbyam sutra is the base sutra used in Vedic multiplier. The design was implemented in Verilog HDL using Xilinx Vivado tool and synthesis was done using Cadence Genus tool.

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Section: Carry Select Addermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design and Implementation of High Speed 32-bit MAC Unit

Bharghava ram dinesh,

Vinoth,

Kasyap

2023

J. Phys.: Conf. Ser.

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“…The adders and multipliers are the major functional blocks used in many of Digital signal processing applications [1], [2]. These designs are widely used for real-time signal processing like audio signal processing, video processing, Image processing and data processing applications.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of High Speed Multiply and Accumulation Unit for Digital Signal Processing Applications

Jahan¹,

Kalyani²,

Sai

et al. 2023

IJRITCC

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Unit for Digital Signal Processing Applications Kausar Jahan1, Pala Kalyani2, V Satya Sai3, GRK Prasad4, Syed Inthiyaz5, Sk Hasane Ahammad6 1Department of ECE, Dadi Institute of Engineering and Technology Anakapalle, Andhra Pradesh, India 2Department of ECE, Vardhaman College of Engineering Kacharam, Shamshabad, India 3Department of ECE, Koneru Lakshmaiah Education Foundation Guntur, India-522502 4Department of ECE, Koneru Lakshmaiah Education Foundation Guntur, India-522502 5Department of ECE, Koneru Lakshmaiah Education Foundation Guntur, India-522502 6Department of ECE, Koneru Lakshmaiah Education Foundation Guntur, India-522502 Abstract—The fundamental component used in many of the Digital signal Processing (DSP) applications are Multiply and Accumulation Unit (MAC). In the literature, a multiplier consists of greater number of full adders and half adder in partial product reduction stage, which increases the hardware complexity and critical path delay to MAC unit. To overcome this problem, two novel multipliers are proposed in this article. The proposed multipliers are designed and implemented in hardware, which reduces the circuit complexity and improves the overall performance of the MAC unit with less delay. The proposed multipliers are compared with the 4-bit existing designs and observed that the number of slices Look Up Tables (LUTs) are minimized from 113 to 43, Slices are reduced from 46 to 14, Full Adders (FAs) are lessened from 28 to 23, bonded Input Output Blocks (IOBs) and Half Adders (HAs) were not altered. The time delay is reduced from 14.251ns to 7.876ns. The proposed multipliers are compared in the literature with the 8-bit multiplier, then the number of Slice LUTs are reduced from 510 to 231, Slices are reduced from 218 to 113, FAs are reduced from 120 to 110, HAs are reduced from 56 to 39, time delay is reduced from 26.228ns to12.748ns, but bonded IOBs count remains same. The synthesis and simulations results are verified by using Xilinx ISE 14.7 version tool.

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