Design of MRAM-Based Magnetic Logic Circuits

Turvani, Giovanna; Bollo, Matteo; Vacca, Marco; Cairo, Fabrizio; Zamboni, Maurizio; Graziano, Mariagrazia

doi:10.1109/tnano.2016.2641444

“…In Reference [5] it is proposed a different way to implement Nano Magnetic Logic (NML) exploiting the MRAM structure. Since the basic concept of the NML technology is the transmission of information through magnetodynamic interaction between neighbouring magnets, the MRAM structure has been modified so that MTJs could interact with each other.…”

Section: Magnet-basedmentioning

confidence: 99%

Data Processing and Information Classification—An In-Memory Approach

Andrighetti

¹

,

Turvani

²

,

Santoro

³

et al. 2020

Sensors

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To live in the information society means to be surrounded by billions of electronic devices full of sensors that constantly acquire data. This enormous amount of data must be processed and classified. A solution commonly adopted is to send these data to server farms to be remotely elaborated. The drawback is a huge battery drain due to high amount of information that must be exchanged. To compensate this problem data must be processed locally, near the sensor itself. But this solution requires huge computational capabilities. While microprocessors, even mobile ones, nowadays have enough computational power, their performance are severely limited by the Memory Wall problem. Memories are too slow, so microprocessors cannot fetch enough data from them, greatly limiting their performance. A solution is the Processing-In-Memory (PIM) approach. New memories are designed that can elaborate data inside them eliminating the Memory Wall problem. In this work we present an example of such a system, using as a case of study the Bitmap Indexing algorithm. Such algorithm is used to classify data coming from many sources in parallel. We propose a hardware accelerator designed around the Processing-In-Memory approach, that is capable of implementing this algorithm and that can also be reconfigured to do other tasks or to work as standard memory. The architecture has been synthesized using CMOS technology. The results that we have obtained highlights that, not only it is possible to process and classify huge amount of data locally, but also that it is possible to obtain this result with a very low power consumption.in slow accesses compared to processors computing speed. This discrepancy in performance harms the computing abilities of the CPU, since the memory cannot provide data as quickly as required by the CPU. This problem is called Von Neumann bottleneck or Memory Wall. The idea that took form to solve this problem is to null the distance between processor and memory, removing the cost of data transfer and create a unit which is capable of storing information and of performing operation on them. This idea takes the name of Processing-in-Memory.Many in literature have approached the "in-memory" idea. Some narrowing the physical distance between memory and computation unit by creating and stacking different layers together. But even if the two units are moved very close to each other, they are still distinct components. Others exploited intrinsic functionality of the memory array or slightly modified peripheral circuitry to perform computation.Among the many example provided by literature, one of the best fitting representative of the PIM concept is presented in Reference [1]. In this work the proposed architecture is a memory array in which the cell itself is capable of performing logical operations aimed at solving Convolutional Neural Networks (CNN). In this paper, our main goal is to introduce a proper example of Processing-in-Memory, choosing Bitmap Indexing as an application around which the architecture is shaped. In th...

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“…In [5] it is proposed a different way to implement Nano Magnetic Logic exploiting the MRAM structure. Since the basic concept of the NML technology is the transmission of information through magnetodynamic interaction between neighbouring magnets, the MRAM structure has been modified so that MTJs could interact with each other.…”

Section: Magnet-basedmentioning

confidence: 99%

Data Processing and Information Classification: An In-Memory Approach

Andrighetti

¹

,

Turvani

²

,

Santoro

³

et al. 2020

Preprint

Self Cite

1

0

View full text Add to dashboard Cite

To live in the information society means to be surrounded by billions of electronic devices full of sensors that constantly acquire data. This enormous amount of data must be processed and classified. A solution commonly adopted is to send these data to server farms to be remotely elaborated. The drawback is a huge battery drain due to high amount of information that must be exchanged. To compensate this problem data must be processed locally, near the sensor itself. But this solution requires huge computational capabilities. While microprocessors, even mobile ones, nowadays have enough computational power, their performance are severely limited by the Memory Wall problem. Memories are too slow, so microprocessors cannot fetch enough data from them, greatly limiting their performance. A solution is the Processing-In-Memory (PIM) approach. New memories are designed that are able to elaborate data inside them eliminating the Memory Wall problem. In this work we present an example of such system, using as a case of study the Bitmap Indexing algorithm. Such algorithm is used to classify data coming from many sources in parallel. We propose an hardware accelerator designed around the Processing-In-Memory approach, that is capable of implementing this algorithm and that can also be reconfigured to do other tasks or to work as standard memory. The architecture has been synthesized using CMOS technology. The results that we have obtained highlights that, not only it is possible to process and classify huge amount of data locally, but also that it is possible to obtain this result with a very low power consumption.

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“…Indeed, MTJs are controlled by three control signals: the bit line, the source line, and the word line. Different combinations of these three signals lead to different logic states [15,16]. This kind of approach leads to a lower power consumption and to more sophisticated control over the magnets.…”

Section: Spin-transfer Torque (Stt) Clockmentioning

confidence: 99%

“…This option is not available for in-plane NML, because it is not possible to generate a local magnetic field that influences only a single magnet. In the STT case, metal lines must be connected to the top and bottom of the MTJ [15] in order to drive a current through each MTJ. The same structure can be used for the magneto-elastic clock, but the energy consumption in this case is far lower [8], therefore leading to high-speed, low-power NML circuits.…”

Section: Proposed Structure For Independent Control Of Piezo-nml Devicesmentioning

confidence: 99%

Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits

Turvani

¹

,

D’Alessandro

²

,

Vacca

³

2018

JLPEA

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Among all “beyond CMOS” solutions currently under investigation, nanomagnetic logic (NML) technology is considered to be one of the most promising. In this technology, nanoscale magnets are rectangularly shaped and are characterized by the intrinsic capability of enabling logic and memory functions in the same device. The design of logic architectures is accomplished by the use of a clocking mechanism that is needed to properly propagate information. Previous works demonstrated that the magneto-elastic effect can be exploited to implement the clocking mechanism by altering the magnetization of magnets. With this paper, we present a novel clocking mechanism enabling the independent control of each single nanodevice exploiting the magneto-elastic effect and enabling high-speed NML circuits. We prove the effectiveness of this approach by performing several micromagnetic simulations. We characterized a chain of nanomagnets in different conditions (e.g., different distance among cells, different electrical fields, and different magnet geometries). This solution improves NML, the reliability of circuits, the fabrication process, and the operating frequency of circuits while keeping the energy consumption at an extremely low level.

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Design of MRAM-Based Magnetic Logic Circuits

Cited by 8 publications

References 49 publications

Data Processing and Information Classification—An In-Memory Approach

Data Processing and Information Classification—An In-Memory Approach

Data Processing and Information Classification: An In-Memory Approach

Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits

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