Design of Multi-Stacked CMOS mm-Wave Power Amplifiers for Phased Array Applications Using Triple-Well Process

Montaseri, Mohammad Hassan; Vuohtoniemi, Risto; Aikio, Janne; Rahkonen, Timo; Pärssinen, Aarno

doi:10.1109/norchip.2018.8573452

Cited by 2 publications

(1 citation statement)

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“…The dimensioning of the mentioned capacitors was designed so that inter-stage matching, i.e. R opt = V DS DC /I D DC [28], was perfectly done [4]- [20] and [23]- [27].…”

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confidence: 99%

Analysis and Design of Capacitive Voltage Distribution Stacked MOS Millimeter-Wave Power Amplifiers

Montaseri

Aikio

Rahkonen

et al. 2022

IEEE Trans. Circuits Syst. I

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Stacked MOS power amplifiers (PA) are commonly 1 used in SOI nodes but also have the potential to be realized in 2 bulk CMOS nodes. In this paper they are analyzed in millimeter 3 wave regimes. The study focuses on the key limiting factors and in 4 particular the optimum number of transistors from which the key 5 performance parameters such as maximum possible operating 6 frequency, output power, and efficiency are achieved. Based on 7 the analysis, design trade-offs of stacked MOS PAs are presented. 8 The frequency dependency of the optimum load presented to 9 each stack is analyzed to express the overall performance of 10 the mentioned PA topologies as a new optimization method. 11 Additionally, it is shown how the optimal load variations trans-12 late into amplitude-to-amplitude/phase (AM-AM/PM) conversion 13 distortions. The validity of the analysis is examined against 14 simulations. The simulations are performed based on 8M1P 15 CMOS 28nm technology and electromagnetic simulations in ADS 16 Momentum.

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“…The dimensioning of the mentioned capacitors was designed so that inter-stage matching, i.e. R opt = V DS DC /I D DC [28], was perfectly done [4]- [20] and [23]- [27].…”

mentioning

confidence: 99%