Design of Multiplier for Medical Image Compression Using Urdhava Tiryakbhyam Sutra

Suma, Suma; Sridhar, V.

doi:10.11591/ijece.v6i3.pp1140-1151

Cited by 6 publications

(4 citation statements)

References 11 publications

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“…Suma and Sridhar 8 introduced the Huffman compression system, which conducts crossover and vertical multiplication and eliminates superfluous data without altering the image and is dependent on the Urdhava Tiryakbhyam method. By reducing the clock frequency, the power consumption for compressing color and gray medical images is increased.…”

Section: Related Workmentioning

confidence: 99%

RETRACTED: Efficient intelligent compression and recognition system-based vision computing for computed tomography COVID images

Abbas

2022

J. Electron. Imag.

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Computed tomography (CT) image-based medical recognition is extensively used for COVID recognition as it improves recognition and scanning rate. A method for intelligent compression and recognition system-based vision computing for CT COVID (ICRS-VC-COVID) was developed. The proposed system first preprocesses lung CT COVID images. Segmentation is then used to split the image into two regions: nonregion of interest (NROI) with fractal lossy compression and region of interest with context tree weighting lossless. Subsequently, a fast discrete curvelet transform (FDCT) is applied. Finally, vector quantization is implemented through the encoder, channel, and decoder. Two experiments were conducted to test the proposed ICRS-VC-COVID. The first evaluated the segmentation compression, FDCT, wavelet transform, and discrete curvelet transform (DCT). The second evaluated the FDCT, wavelet transform, and DCT with segmentation. It demonstrates a significant improvement in performance parameters, such as mean square error, peak signal-to-noise ratio, and compression ratio. At similar computational complexity, the proposed ICRS-VC-COVID is superior to some existing techniques. Moreover, at the same bit rate, it significantly improves the quality of the image. Thus, the proposed method can enable lung CT COVID images to be applied for disease recognition with low computational power and space.

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Section: Related Workmentioning

confidence: 99%

RETRACTED: Efficient intelligent compression and recognition system-based vision computing for computed tomography COVID images

Abbas

2022

J. Electron. Imag.

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“…In addition to that; power consumption and size area dimension are important design factors for any chip designers. Since the multiplier is the key element for most computing processes and other applications such as medical image compression [1], therefore; the improvement of multipliers became a researcher's target.…”

Section: Introductionmentioning

confidence: 99%

A novel approach of multiplier design based on BCD decoder

Alkurwy¹

2019

IJEECS

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A novel approach of multiplier design is presented in this paper. The design idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3 3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A5: A0], using a Karnaugh map. Then, the 3 3-bits multiplier circuit is used to implement the 6x6- and 12x 12-bit multipliers. Comparing with a conventional multiplier, the proposed design outperformed in terms of the time delay by a 32% and 41.8% respectively. It is also reduced the combinational adaptive look-up-tables (ALUTs) by 24.6%, and 46% for both multipliers. Both overmentioned advantages make the proposed multipliers more attractive and suitable for high-speed digital systems

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“…They are also applicable to complex problems involving a large number of mathematical operations. The technique has been used in various domains including the design of low‐power image compression [2] and in signal processing domain [3, 4]. The application of a Vedic multiplier in encryption/decryption algorithm, Infinite Impulse Response (IIR) filters, and floating‐point mathematics has been explored in the literature [5, 6].…”

Section: Introductionmentioning

confidence: 99%

Gate diffusion input based 4‐bit Vedic multiplier design

Garg

Joshi

2018

IET Circuits, Devices & Systems

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A multiplier is one of the key hardware blocks in most of the processors. Multiplication is a lengthy, time-consuming task. Vedic multiplication in field programmable gate array implementation has been proven effective in reducing the number of steps and circuit delay. Conventionally at the circuit level, complementary metal oxide semiconductor (CMOS) logic is used to design a multiplier. In CMOS circuits, the area is always an issue. Gate diffusion input (GDI)-based logic has been explored in the literature to reduce the number of transistors for various logic functions. Thus, Vedic mathematics, on the one hand, simplifies the multiplication process and reduces the delay; while on the other hand, GDI technique helps in minimising the transistor count (TC) and reduction in power. Therefore, this study puts forth a GDI logic-based 4-bit Vedic multiplier. To study the effectiveness of the GDI logic, the transient response of a 2-bit Vedic multiplier using CMOS and GDI is compared. For the 4-bit Vedic multiplier, two design approaches are taken into consideration. The performance of these circuits is analysed in terms of average power dissipation, delay, and TC. The effect of supply voltage scaling is also studied. The circuit simulations are carried out at 130 nm for bulk metal oxide semiconductor field effect transistor predictive technology model-based device parameters.

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Design of Multiplier for Medical Image Compression Using Urdhava Tiryakbhyam Sutra

Cited by 6 publications

References 11 publications

RETRACTED: Efficient intelligent compression and recognition system-based vision computing for computed tomography COVID images

RETRACTED: Efficient intelligent compression and recognition system-based vision computing for computed tomography COVID images

A novel approach of multiplier design based on BCD decoder

Gate diffusion input based 4‐bit Vedic multiplier design

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