Design of neuro-fuzzy controller for the speed control of a DC servo motor

Kang, Young-Ho; Kim, Lark-Kyo

doi:10.1109/icems.2001.971780

Cited by 5 publications

(2 citation statements)

References 3 publications

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“…Implementations of large control algorithms with many variables are usually carried out by software, such as mechanical or thermal processes, which typically operate below K FLIPS rate (FLIPS stands for fuzzy logic inferences per second) [15,8]. It is not fast enough for many highspeed control problems such as automotive engines control and power systems [5,17]. Special-purpose hardware could be necessary to perform better than the previous approaches.…”

Section: Introductionmentioning

confidence: 99%

Neuro-fuzzy system with high-speed low-power analog blocks

Wang

Jin

2006

Fuzzy Sets and Systems

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Section: Introductionmentioning

confidence: 99%

Neuro-fuzzy system with high-speed low-power analog blocks

Wang

Jin

2006

Fuzzy Sets and Systems

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“…However, if faster processes are going to be faced, as those in motion control and power systems, special purpose hardware could be necessary or perform better than the previous approach. To cope with complex control tasks in the range of milliseconds, general purpose microprocessors or DSPs, or those with a special set of instructions are the best choice [5] [6]. However, to manage delays of few milliseconds and down to the microsecond and even nanosecond range, special purpose ASICs are required [7][8] [9].…”

mentioning

confidence: 99%

Neuro-fuzzy chip to handle complex tasks with analog performance

Navas-González

Vidal‐Verdú

Rodríguez-Vázquez

2003

IEEE Trans. Neural Netw.

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This Paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input-output delay and precision performs as a fully analog implementation. However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core [1]. Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture are smaller than those of its purely analog counterparts simply because most rules are implemented through programming. The Paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype. This prototype, called MFCON, has been realized in a CMOS 0.7µm standard technology. It has two inputs, implements 64 rules and features 500ns of input to output delay with 16mW of power consumption. Results from the chip in a control application with a DC motor are also provided.

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Experimental verification of chopper fed DC series motor with ANN controller

Muruganandam¹,

Madheswaran²

2012

Front. Electr. Electron. Eng.

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Design of neuro-fuzzy controller for the speed control of a DC servo motor

Cited by 5 publications

References 3 publications

Neuro-fuzzy system with high-speed low-power analog blocks

Neuro-fuzzy system with high-speed low-power analog blocks

Neuro-fuzzy chip to handle complex tasks with analog performance

Experimental verification of chopper fed DC series motor with ANN controller

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