Design of Novel Hardware Architecture for Fully Homomorphic Encryption Algorithms in FPGA for Real-Time Data in Cloud Computing

Behera, Sagarika; Prathuri, Jhansi Rani

doi:10.1109/access.2022.3229892

Cited by 6 publications

(7 citation statements)

References 29 publications

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“…A novel hardware architecture for the BV FHE scheme is proposed in [15]. The paper also covers the simulation of FPGA-based design using the Questasim simulator and implementation in Intel FPGA using the Quartus tool.…”

Section: Relevant Workmentioning

confidence: 99%

“…Decryption is performed by evaluating the input ciphertext in level l on the secret key to generate an approximate value of the plaintext message as given in (15).…”

Section: System Architecturementioning

confidence: 99%

“…The design diagram for NTT from our previous work [15] is shown in Figure 8. The entire data stream is split into three blocks, as seen in the figure.…”

Section: Design Diagram For Number Theoretic Transformmentioning

confidence: 99%

“…The frequency achieved for 32-channel CKKS-KNN is 300 MHZ, which is faster compared to the 196 MHZ of single-channel and 250 MHZ of [39,40]. NTT-based polynomial multiplications for FPGA implementation have been published in [15,41,42] to speed up the encryption and decryption process. Polynomial multiplication is a computationally demanding technique that is frequently employed in homomorphic encryption and decryption operations.…”

mentioning

confidence: 99%

“…The FPGA used in [41] is Zynq Ultrascale+ and Virtrex 7 is used in [42]. We have used Agilex 7 FPGA in our previous work [15] and in this current work. However, an attempt has been made to compare logic utilization and latency.…”

mentioning

confidence: 99%

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FPGA-Based Acceleration of K-Nearest Neighbor Algorithm on Fully Homomorphic Encrypted Data

Behera,

Prathuri

2024

Cryptography

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The suggested solution in this work makes use of the parallel processing capability of FPGA to enhance the efficiency of the K-Nearest Neighbor (KNN) algorithm on encrypted data. The suggested technique was assessed utilizing the breast cancer datasets and the findings indicate that the FPGA-based acceleration method provides significant performance improvements over software implementation. The Cheon–Kim–Kim–Song (CKKS) homomorphic encryption scheme is used for the computation of ciphertext. After extensive simulation in Python and implementation in FPGA, it was found that the proposed architecture brings down the computational time of KNN on ciphertext to a realistic value in the order of the KNN classification algorithm over plaintext. For the FPGA implementation, we used the Intel Agilex7 FPGA (AGFB014R24B2E2V) development board and validated the speed of computation, latency, throughput, and logic utilization. It was observed that the KNN on encrypted data has a computational time of 41.72 ms which is 80 times slower than the KNN on plaintext whose computational time is of 0.518 ms. The main computation time for CKKS FHE schemes is 41.72 ms. With our architecture, we were able to reduce the calculation time of the CKKS-based KNN to 0.85 ms by using 32 parallel encryption hardware and reaching 300 MHz speed.

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Section: Relevant Workmentioning

confidence: 99%

“…Decryption is performed by evaluating the input ciphertext in level l on the secret key to generate an approximate value of the plaintext message as given in (15).…”

Section: System Architecturementioning

confidence: 99%

“…The design diagram for NTT from our previous work [15] is shown in Figure 8. The entire data stream is split into three blocks, as seen in the figure.…”

Section: Design Diagram For Number Theoretic Transformmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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