Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs

Rodríguez, Alonso Mateos; Valverde, Juan; Torre, Eduardo de la

doi:10.1109/reconfig.2015.7393297

Cited by 5 publications

(4 citation statements)

References 18 publications

(19 reference statements)

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“…The first analysis of the solution space exploration capabilities of the ARTICo 3 architecture was presented in [ 45 ], were the data-parallel execution model that enables transparent scalability was also introduced. However, the flow relied on custom ad-hoc bare-metal software libraries and manual hardware implementation techniques that were application-specific and needed to be tailored for each scenario.…”

Section: The Artico 3 Frameworkmentioning

confidence: 99%

FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework

Rodríguez

Valverde

Portilla

et al. 2018

Sensors

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Cyber-Physical Systems are experiencing a paradigm shift in which processing has been relocated to the distributed sensing layer and is no longer performed in a centralized manner. This approach, usually referred to as Edge Computing, demands the use of hardware platforms that are able to manage the steadily increasing requirements in computing performance, while keeping energy efficiency and the adaptability imposed by the interaction with the physical world. In this context, SRAM-based FPGAs and their inherent run-time reconfigurability, when coupled with smart power management strategies, are a suitable solution. However, they usually fail in user accessibility and ease of development. In this paper, an integrated framework to develop FPGA-based high-performance embedded systems for Edge Computing in Cyber-Physical Systems is presented. This framework provides a hardware-based processing architecture, an automated toolchain, and a runtime to transparently generate and manage reconfigurable systems from high-level system descriptions without additional user intervention. Moreover, it provides users with support for dynamically adapting the available computing resources to switch the working point of the architecture in a solution space defined by computing performance, energy consumption and fault tolerance. Results show that it is indeed possible to explore this solution space at run time and prove that the proposed framework is a competitive alternative to software-based edge computing platforms, being able to provide not only faster solutions, but also higher energy efficiency for computing-intensive algorithms with significant levels of data-level parallelism.

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Section: The Artico 3 Frameworkmentioning

confidence: 99%

FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework

Rodríguez

Valverde

Portilla

et al. 2018

Sensors

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“…In one of the examples proposed, the ARTICo 3 architecture [32] is used. ARTICo 3 permits to manage and set, dynamically, reconfigurable hardware accelerators making use of the Dynamic and Partial Reconfiguration (DPR).…”

Section: The Hardware Architecture: Articomentioning

confidence: 99%

“…Its use has been already demonstrated in the Cyber-Physical System field where a fair trade-off among performance, dependability and energy consumption is achieved thanks to a runtime adaptable bus architecture [33]. In this paper we are not focusing the attention on the benefits/disadvantages that this hardware structure brings and (1)further details on the implementations, (2)software APIs, (3)applications developed and (4)performance/power-consumption measurements are out of the scope of this work and are remanded to the bibliography [32] [33]. However, in Fig 3, a stylized view of the whole system is given, where it is possible to identify the Processing System of the UltraScale+ (with the inclusion of two main physical cores) and how it is connected to the Programmable Logic (PL).…”

Section: The Hardware Architecture: Articomentioning

confidence: 99%

A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures Using PAPI

Suriano

Madroñal

Rodríguez

et al. 2018

2018 13th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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In this work, a standard and unified method for monitoring hardware accelerators in Reconfigurable Computing Architectures is proposed, based on a standard software monitoring interface. The open source Performance Application Programming Interface (PAPI) library is commonly used in the field of High Performance Computing and aims at providing event information directly extracted from a set of Performance Monitor Counters. Important events such as data and instruction cache misses, hardware interrupts, etc. are collected to analyze and profile applications to pinpoint the contingent bottlenecks. In other words, it serves as a "Hardware Abstraction layer" for applications running in the user-space. In this paper, its use is extended by proposing a method to target custom Performance Hardware Registers on accelerators built upon an FPGA. Furthermore, portability and standardization are discussed and the overhead associated with PAPI use is evaluated. Two hardware examples are proposed to evaluate this approach: a simple counter and an infrastructure for hardware accelerators called ARTICo 3 .

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“…In this sense it may be extremely beneficial to jointly exploit coarse grained reconfigurable accelerators (limiting their inactivity with switch off policies) and dynamic partial reconfiguration to foster components reuse, replacing inactive slots by other elements that need to be executed. The Artico3 architecture [9] is to be used for HW acceleration, provides a method for runtime selecting a variable number of HW accelerators with adaptable module redundancy, performance and energy consumption. Artico3 will be adapted to other models of computation such as dataflow, combined with just-in-time compilation to provide functionality, performance and energy adaptation.…”

Section: B Runtime Autonomous Enginementioning

confidence: 99%

Cross-layer design of reconfigurable cyber-physical systems

Masin¹,

Palumbo

Myrhaug³

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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layers. Moreover, because of inherent interdependence, the layers must communicate a lot. To handle these challenges CERBERO approach leverages on two main pillars:• a model-centric approach to the scenario and system definition, where all the functional, physical, and network components as well as the environment are kept into consideration along with the properties that have to be addressed. • a multi-layer runtime adaptation strategy for CPS, embodied within a high-level self-adaptation engine capable of reacting to external stimulus and autonomously adapting to the evolution of the scenario or constraints. These two pillars, presented in Sect. II-A and Sect. II-B, respectively, contribute to determine the CERBERO continuous design and operational framework for highly interconnected systems presented in Sect. II-C. A. Model-Centric ApproachComputational, physical and communication layers within CERBERO are going to be cross-optimized, taking into consideration that they are intrinsically concurrent, among each other and internally. To answer the current lack of a comprehensive modeling strategy for heterogeneous CPS, CER-BERO intends to implement a component-oriented approach, with dedicated model-to-model mapping and synchronization interfaces with feedback loops. This strategy is meant to concurrently handle time-continuum and event-driven models that need to coexist, since they are representative of both the physical and the computing aspects of the system, while asynchronous, partially-ordered discrete actions or clock-driven time slots describe the communication layer. In order to reconcile these divergent models, and ensure interoperability and communication between components, we plan to incorporate the following elements in the CERBERO framework: 1) Functional and non-functional requirements management:Generic requirements (e.g., security, energy, dependability) and highly application-specific ones (e.g., the availability of charging points on EV network) are handled. By studying and defining adequate description languages and by providing a generic library of reusable Key Performance Indicators (KPIs) models, we intend to tackle adaptivity in different scenarios and models re-use in consecutive design and operational cycles. Such KPIs also offer an objective and quantitative analysis of the system. 2) Entity/components cross-optimization and validation:Dataflow Models of Computation (MoCs) provide precise semantics to express and, consequently, exploit the intrinsic computing problem parallelism. As demonstrated in literature [8], they are extremely suitable to model both hardware (HW) and software (SW) components at a high level of abstraction, and to perform trade-off analysis and components cross-optimization. On the other hand, state based stochastic algebraic and differential inequalities are suited to represent a large class of dynamic systems. The combination of these models is meant to input effective design space exploration (DSE) and multi-objective

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Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs

Cited by 5 publications

References 18 publications

FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework

FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework

A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures Using PAPI

Cross-layer design of reconfigurable cyber-physical systems

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