2015
DOI: 10.1109/tc.2015.2401019
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Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction

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Cited by 11 publications
(1 citation statement)
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“…UE to manufacturing process variability, faults are inevitable in integrated circuit (IC) fabrication [1]. The faults in IC can mix with the system intrinsic faults [2]- [4] to make fault detection more complicated and costly [5]- [7].…”
Section: Introductionmentioning
confidence: 99%
“…UE to manufacturing process variability, faults are inevitable in integrated circuit (IC) fabrication [1]. The faults in IC can mix with the system intrinsic faults [2]- [4] to make fault detection more complicated and costly [5]- [7].…”
Section: Introductionmentioning
confidence: 99%