Abstract:The stability and power consumption of SRAM cell are the important factors in current technologies due to variability and voltage scaling. It has become a part of system-on-chip in modern VLSI designs. The existing SRAM cell designs are power hungry and have low performance for fast computing applications. In the proposed work a low power 8T SRAM cell is designed based on power gating mechanism. The Conventional 6T SRAM cell is very much prone to noise during read operation. To overcome the read SNM problem in… Show more
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