Design of Proficient Two Operand Adder Using Hybrid Carry Select Adder with FPGA Implementation

Thamizharasan, V.; Kasthuri, N.

doi:10.1080/03772063.2022.2071771

Cited by 9 publications

(6 citation statements)

References 24 publications

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“…Since Koggestone have a less delay and Brent kung is having a less area utilization. The combination of BK adder(For Cin = 0) and Koggestone adder(for Cin = 1) is named as Han Carlson adder [9].…”

Section: Review Of Additionmentioning

confidence: 99%

Design of Efficient Binary Multiplier Architecture using Hybrid Compressor with FPGA implementation

Thamizharasan,

Parthipan

2023

Preprint

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In emerging digital world, the high-performance arithmetic computing module with low power and reduced area are required to compute the Signal processing application operations. In that signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and arithmetic & logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplication and it used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor for application of Cryptography and signal processing system. The proposed hybrid compressor-based multiplier is designed and implemented in FPGA (spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on CLA (28.49%), Vedic Multiplier based on RCA (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on HCA (20.10%) and Hybrid multiplier using CSELA (17.81%) and Hybrid Vedic Multiplier (7.15%).

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Section: Review Of Additionmentioning

confidence: 99%

Design of Efficient Binary Multiplier Architecture using Hybrid Compressor with FPGA implementation

Thamizharasan,

Parthipan

2023

Preprint

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“…In order to find a solution to this issue, the focus of this article will be on developing a novel Truncated multiplier approach that is founded on the Hybrid PPA methodology. At the outset, a one-of-a-kind Hybrid PPA that was assembled from HSG, FSG, HCG, and HSG building blocks was developed [7]. In addition to that, the Hybrid PPA has the capabilities of SQRT enhancements.…”

Section: Introductionmentioning

confidence: 99%

Implementation of low power N-bit hybrid parallel prefix adder using Xilinx-ISE

Gopathoti¹,

Sruthi²

2023

IJSMEM

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Recently, digital circuitry has demanded a decrease in space and power by decreasing time while simultaneously improving performance in speed. This has resulted in a need for more efficient use of the available space. Adders are fundamental components that are used in the construction of digital circuits. As a consequence of this, the performance of adders has to be improved in order to enhance the performance of integrated circuits that are used in the real world. The creation of a novel parallel prefix adder (PPA) architecture known as Hybrid PPA is the primary topic of this article. Hybrid PPA makes use of full carrier generation (FCG), full sum generation (FSG), half carry generation (HCG), and half sum generation (HSG) blocks. In addition to this, the N-bit Hybrid-PPA is constructed with features that may be reconfigured, and these features utilise square root additions through modified sum carry selection (MSCS). In addition, the implementation of multiplexer switching logic, which selects the whole sum bits and carry bits in a high-speed manner, reduces the amount of propagation time necessary for the generation of the sum and carry output. The results of the simulation show that using the proposed Hybrid PPA results in a reduction in area, latency, and power consumption when compared to using basic adders or approaches that are considered to be state of the art.

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“…The most crucial adder block characteristics are area and propagation delays [22]. In many signal-processing applications, addition is a crucial arithmetic operation [23]. Consequently, power usage turns into a significant issue in the design of digital circuits.…”

Section: Introductionmentioning

confidence: 99%

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

Battini

PASHYA

Sivani

2023

Preprint

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Conventional carry select adder (CCSA) uses a multiplexer in the final stage to select either an excess-1 result or a normal result. To improve the delay and number of transistors a new topology is Proposed (PCSA) that uses only a single type of cell i.e., a 2 − 1 multiplexer. The 2 − 1 multiplexer is constructed in CMOS and TGL logic styles using 18nm FinFETs. The sub-blocks such as half adder and excess-1 circuit used in this PCSA is realized using only a 2:1 multiplexer. Due to the usage of a single type 2:1 multiplexer, the PCSA exhibits better circuit regularity. The new topology of PCSA is designed using FinFET-based TGL and CMOS styles. All the adders such 4- and 8-bit are designed, simulated, and analyzed using Cadence Virtuoso, ADEL, and ADEXL at 18nm FinFET technology. The result analysis reveals that the speed performance and the number of transistors of 8-bit PCSA are better by 44.02% and 4% respectively compared to existing adders.

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Design of Proficient Two Operand Adder Using Hybrid Carry Select Adder with FPGA Implementation

Cited by 9 publications

References 24 publications

Design of Efficient Binary Multiplier Architecture using Hybrid Compressor with FPGA implementation

Design of Efficient Binary Multiplier Architecture using Hybrid Compressor with FPGA implementation

Implementation of low power N-bit hybrid parallel prefix adder using Xilinx-ISE

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

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