Design of QAM in 45nm Using Cadence Tool

Hosamani, Ravi; Tonape, Govindaraj; Mannur, Harshavardhana; Neelagund, Basavaraj

doi:10.1109/asiancon55314.2022.9909362

Cited by 2 publications

(1 citation statement)

References 13 publications

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“…Simulation, synthesis and implementation environment All the designs are extensively simulated using Cadence NC Launch [29]. The synthesis and implementation are carried out using Cadence Genus [30] and [31] and Innovus tools [32] and [33] respectively. A 90nm process technology library is used while synthesis and implementation.…”

Section: Resultsmentioning

confidence: 99%

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Battini

Bikshalu²,

Sivani³

2023

Eng. Res. Express

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This paper proposes a novel architecture of novel excess-1 adder basedCarry Select Adder (M2CSA) using single leaf cell i.e., 2-1 Multiplexer. The proposed4-, 8-, 16-, 32-, 64-bit M2CSAs use 2-1 Multiplexers only. The complex gates suchas XOR gates are completely eliminated which exist in existing Carry Select Adders(CaSeAs). A 64-bit M2CSA is distinctly decomposed for maintaining excellent cellregularity that uses one type of 2-1 Multiplexer cell. Ripple carry adder block inexisting designs are replaced with half adders by reducing the carry propagation tocertain extent. At the outset the speed of M2CSA is improved by overcoming carrypropagation through adder blocks, especially in 32- and 64-bit adders. The area isthe major concern for CaSeAs; is also reduced for M2CSAs by maintaining the cellregularity. The M2CSA and existing CaSeAs are designed using Verilog HDL. Thefunctional testing of all the designs is carried out using Cadence NCLaunch. All thedesigns are synthesized & implemented using Cadence Genus and Innovus respectivelyat 90nm technology node. The final ASIC layout of 64-bit M2CSA is more compact interms of area by an average of 17% compared to existing designs. The result analysisand comparison reveal that M2CSAs are better in terms of speed and power dissipationby 20% and 19% respectively. Therefore, M2CSA is best suitable to low-power, low area and high-speed applications

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Section: Resultsmentioning

confidence: 99%

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Battini

Bikshalu²,

Sivani³

2023

Eng. Res. Express

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Design of an integrated circuit with blanking technique for neural signal recording based on CMOS

Zhu,

Mo,

Liu

2023

J. Phys.: Conf. Ser.

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Neural signals play a crucial role in unraveling the mysteries of the nervous system. However, due to their minute amplitudes in the range of microamperes and microvolts, recording these signals poses significant challenges, largely stemming from their vulnerability to noise interference. Thus, the development of neural signal acquisition circuits holds paramount importance. This paper presents a successful endeavor in designing an integrated circuit using 0.18um CMOS technology, which exhibits exceptional accuracy in recording neural signals. The circuit employs a combination of amplifiers and filters, while incorporating the innovative blanking technology to effectively eliminate unwanted noise. Remarkably, this design accomplishes an impressive gain of 88.437dB. Consequently, the circuit enables the accurate capture of nerve signals, thereby positioning itself as an ideal candidate for implantable neural signal detection devices. With its ability to overcome the hurdles associated with signal sensitivity and noise interference, this integrated circuit represents a significant advancement in the field of neural signal acquisition, holding immense potential for further exploration and application in neuroscientific research and medical interventions.

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Design of QAM in 45nm Using Cadence Tool

Cited by 2 publications

References 13 publications

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Design of an integrated circuit with blanking technique for neural signal recording based on CMOS

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