Design of Real-Time Hardware for Edge Detection

Lee, Chang-Yong; Kim, Young-Hyung; Lee, Yong-Hwan

doi:10.1109/csci46756.2018.00073

Cited by 4 publications

(1 citation statement)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Vivado constitutes a planning software platform specifically designed for Xilinx FPGAs and is interdependently linked with the layouts of said chips. Consequently, it is unsuitable for deployment with FPGAs furnished by alternative vendors [13][14][15][16][17][18][19] 3.3. Verilog Code for Image Processing.…”

Section: Xilinx Vivado the Vivado Plan Suite Developed Bymentioning

confidence: 99%

Implementation of Image Enhancement and Edge Detection Algorithm on Diabetic Retinopathy (DR) Image Using FPGA

Orthy,

Islam,

Rashid

et al. 2023

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

Diabetic retinopathy (DR) is an ocular ailment that may lead to loss of vision and eventual blindness among individuals diagnosed with diabetes. The blood vessels of the retina, a layer of light-sensitive tissue located at the posterior aspect of the ocular globe, are adversely impacted. The identification of DR entails the utilization of retinal fundus images. The detection of any form of abnormality in the eye through raw fundus images poses a significant challenge for medical practitioners. Hence, it is imperative to engage in the processing of fundus images. This paper delineates several image processing techniques for DR images, including but not limited to, manipulation of brightness levels, application of negative transformation, and utilization of threshold operations. It focuses on elucidating the enhancement techniques that pertain to DR images, which aim to optimize the visual quality of said images in order to facilitate more facile disease detection. The process of detecting edges within DR images is also executed by Sobel edge detection algorithm. In order to successfully execute the aforementioned algorithms, expedient and contemporaneous systems are favored to account for the intricacies of the image processing calculations. The exclusive utilization of software techniques in order to fulfill the prerequisites of advanced algorithms presents a significant challenge, owing to the multifarious processes that are involved in their computation, coupled with an exigent requirement for high processing speeds. The proposed model is utilized to articulate a proficient model for the design and execution of field programable gate array (FPGA)-based image enhancement processes along with the Sobel edge detection algorithm upon DR images. Finally, a Internet Protocol chip is developed that can combine multiple image enhancement operations into a single framework with less complexity.

show abstract