Design of Reed-Solomon (16,12) codec for North American Advanced Train Control System

Shayan, Yousef R.; Le‐Ngoc, Tho; Bhargava, V.K.

doi:10.1109/25.61362

Cited by 15 publications

(3 citation statements)

References 4 publications

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“…However, due to lack of hardware support for finite field multiplications, sophisticated RS codecs are usually slow in software. A software based RS (16,12) coder was presented in [14], in which general-purpose DSP processors or microprocessors were used for programming. If finite-field arithmetic would be implemented in a programmable DSP datapath, the universal RS codecs (and other finite-field based systems) could be easily implemented in software.…”

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confidence: 99%

Approaches to low-power implementations of DSP systems

Parhi

2001

IEEE Trans. Circuits Syst. I

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Abstract-Reduction of power consumption is significantly important for all high-performance digital VLSI systems. This paper reviews several approaches for low-power implementations of building blocks for digital subscriber line (DSL) systems. Low-power implementations of Reed-Solomon (RS) coders, fast Fourier transforms (FFTs), FIR filters, and equalizers, and reduction of power consumption by use of dual supply voltages are addressed. It is shown that use of separate Galois Field functional units for multiply-accumulate and degree reduction can reduce the energy consumption of RS coders dramatically. A hybrid feedforward and feedback commutator scheme-based FFT is shown to require less area and full hardware utilization efficiency. Reduction of switching activity at one or both inputs of the multipliers is a key to reduction of power consumption in FIR filters and equalizers. The switching activity can be reduced by use of transpose structure and by time-multiplexing of an unfolded filter. A well established retiming approach can be generalized to find those noncritical gates which can be operated with lower supply voltages to reduce the overall system power consumption.

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confidence: 99%

Approaches to low-power implementations of DSP systems

Parhi

2001

IEEE Trans. Circuits Syst. I

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“…For example RS codes have been applied to the compact disc (CD) system [l], advanced train control systems [2], the Hubble space telescope [3] and channel coding for compressed video services [4]. RS codes operate over algebraic structures called finite fields, denoted GF @") , and because of the ease with which they can be implemented in digital hardware, these fields are usually restricted to those of the form GF(2'") [5].…”

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confidence: 99%

“…Th% Pp is then { 1, a, a ,a } and from Equation (6) the GTB to the PB is { 1, a , a , a} with = a . Hence if (ao,, al, a2, a3) is the PB representation of a E GF( 2 ) , the GTB of this element is (ao, a3, a2, a l ) which is a simple permutation of the PB coefficients.…”

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confidence: 99%

Generalised triangular basis multipliers for the design of Reed-Solomon codecs

Furness

Benaïssa²,

Fenn³

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation Formerly VLSI Signal Processing

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In this paper a generalised definition of a triangular basis for CF(F) ispresented. This definition is more flexible than the traditional definition and allows a number of triangular bases to be determined to any given basis. The triangular basis to the polynomial basis can then be used which has the simplest basis transformation in modified Hasan-Bhargava multipliers. It is shown that when the defining irreducible polynomial for the field is a trinomial, the triangular basis is a permutation of the polynomial basis elements. Furthermore, if the defining irreducible polynomial is a pentanomial of a certain form, the triangular basis can be obtained from the polynomial basis with a reordering of the coefficients and two GF(2) additions. This new definition of triangularity allows for reduced complexity modified Hasan-Bhargava multipliers to be designed which in turn reduces the hardware complexity of Reed-Solomon codecs using these multipliers. Finally, a simple method of making large hardware savings in Reed-Solomon decoders utilising frequency domain decoding is presented.0-7803-3806-5/97/$10.00 0 1 997 IEEE 202 expense of a hardware increase in the encoder. Similarly in the case of an RS (255,223) code, the saving of 223 constant multipliers equates to a hardware saving of around 3,500 XOR gates when using bit-parallel multipliers at the expense of an increase of 48 XOR gates in the encoder. J J

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