Design of reliable a-Si:H gate driver circuit with high immunity against the vth shift of tft and output fluctuations

Abstract

AC-driving structure is utilized in this new gate driver circuit to suppress V TH shift of a-Si:H TFT. By modulating the biased-stress on pull-down TFT, the floating row lines of panels is effectively eliminated. The results depict this circuit can ensure the longer operating lifetime. Technical SummaryHydrogenated amorphous silicon (a-Si:H) technology is extensively used for manufacturing of active-matrix liquid crystal displays (AM-LCDs) due to its lower cost, mature fabrication process and good uniformity over large area coating [1]- [5]. However, the threshold voltage shift (V TH shift) of a-Si:H TFT, resulting from charge trapping and defect creation under long-term bias stress, is another inevitable phenomenon which would lead to the degradation of a-Si:H TFT [6], [26]. Conventional gate driver circuit suffers from output fluctuations caused by floating row lines and the capacitor coupling effect of pull-up TFT [3]. This drawback may affect image quality of the panels. Thus, employing DC-bias on the pull-down TFT to eliminate floating row lines and output noise was proposed. As a result, the pull-down TFT would critically decay, leading to reduced operating lifetime of the gate driver circuits. To improve this problem, the AC-driving method for gate drivers is employed to hinder the V TH shift of a-Si:H TFT and prevent row lines from floating [4], [5]. By reducing the duty ratios of the gate-bias stress on a-Si:H TFTs, the V TH shift can be effectively retarded in comparison with the condition of DC-bias stress. Noteworthily, the high voltage swing (V SW ) of the clock signal is also a significant factor which will decrease the lifetime of a-Si:H TFTs [7]. Except for reducing duty ratios of clock signals [4], few of researches focus on the influence of V SW when stressing on a-Si:H TFTs. Therefore, this work proposes a new integrated a-Si:H gate driver circuit with AC-driving structure which can be employed for large-size panel applications. Besides, the outputs have high immunity against noise by modulating proper bias stress on pull-down TFT to stabilize the output node. The experiment and simulation results show that the proposed gate driver circuit can successfully provide the row lines with stable outputs, and the V TH shift of pull-down TFT can be suppressed to ensure longer operating time of the circuit.The measurement results of stressing a-Si:H TFTs are shown in Fig. 1. From Fig. 1(a), with continuous high bias stress for 10 minutes at 100 ℃ and 33.3% duty ratio, the current driving capability of TFT is greatly reduced. However, by lowering the voltage swing of bias stress from 40 V (-10 V ~ 30 V) to 10 V (-10 V ~ 0 V), the performance of TFT transfer characteristics are much more excellent than that of the first tested TFT even for sustained tress time of 30 minutes at 100 ℃ and 33.3% duty ratio, as shown in Fig. 1(b). Fig. 2(a) represents the schematic of the proposed circuit and Fig. 2(b)-(I) indicates that the Q [n] node suffers from the capacitor coupling effect of T10. This may result in unst...