Design of robust signal and clock networks

Abstract

As technology scales down into the nanometer region new design challenges emerge. Wire delays become the performance bottleneck in VLSI circuits. Copper is introduced as new wiring material because of its low sheet resistivity, hence low signal propagation delay. The main defect mechanism shifts from shorts to opens due to the different manufacturing process for copper wires. Open defects limit functional yield. Parametric yield decreases because of timing uncertainties emerging from manufacturing variation. Clock skew variation becomes critical because it may shorten the cycle length of the critical path. The variation of signal nets has to be considered simultaneously avoiding overly pessimistic designs. Design techniques which reduce the variation of design parameters avoid over design and increase parametric yield.Whereas tree topologies have been applied due to their minimal wire length, the application of generic routing graphs provides multiple paths to specific sinks. Multiple paths from source to sink increase the robustness against open defects and smoothes the effect of variation. New design techniques applying loops in VLSI wiring networks are the topic of this abstract.Millions of signal communication networks have to be designed on an integrated circuit (IC). Those networks can be classified according to their application. Signal nets connect a driving cell to a plurality of receiving cells. The ports of the cells are referred to as terminals and their physical representations are called pin. If the load of the driving cell is beyond its driving capabilities due to the large fan-out or wire length of the net, repeaters will be inserted and a repeater network is created. A repeater network consists of different nets that propagate the same signal or its inverse. A clock signal synchronizes the whole design. It is distributed via the clock network to all synchronous storage elements in a clock domain.There are four major trends that drive the development of IC circuit design in general and especially the design of onchip communication networks. With the integration of more and more devices per unit area and the demand for higher clock frequencies it is important to minimize the power dissipation and wire congestion on the chip. Additionally, the clock frequency is a constraint and yield is a maximization objective. A decade ago these objectives were adressed by applying routing trees as net topologies. With decreasing feature sizes trees have to be reconsidered because other topologies offer advantages. Topologies containing loops offer some robustness against opens. Additionally, an averaging effect can be exploited if the signal is propagated via multiple signal paths. If the signal arrives early on the fast path and late on the slow path, the arrival time of the signal is averaged. Therefore, loop topologies help to increase functional and parametric yield.The main advantage of trees is their minimal wire length (WL). Topologies containing loops always have an increased WL compared to trees. Extre...