Design of SET tolerant LC oscillators using distributed bias circuitry

Jagtap, Sharayu; Sharma, Dinesh Kumar; Gupta, Shalabh

doi:10.1016/j.microrel.2015.07.017

Cited by 16 publications

(10 citation statements)

References 11 publications

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“…As the proposed fault‐tolerant delay cell utilises parallel transistors instead of single transistor, the small size transistors are selected to keep the operational frequency similar with the non‐redundant RO. With the small size transistors, it is expected that lower number of electron‐hole pairs is produced when SE hit occurs [13]. This phenomenon makes the circuit more tolerable against radiation strikes.…”

Section: Proposed Fault‐tolerant Delay Cellsmentioning

confidence: 99%

“…Current pulse used for circuit level simulations is particle incident with varying linear energy transfer [10]. For the proposed design a pulse with 1ps rise time, 20 ps fall time and 5 mA magnitude are used to generate 100 fC of charge [11, 13]. By injecting this amount of charge to the vulnerable nodes, the output signal is disturbed.…”

Section: Proposed Fault‐tolerant Delay Cellsmentioning

confidence: 99%

“…The larger value of the decoupling resistor is used, the greater improvement in attenuating SET effects is achieved. Thus, the value of series resistor in the tail current circuit cannot be too large, since it is confined by the voltage headroom [13]. A distributed biasing technique can mitigate this problem as described in [13] without any increment in power dissipation or degradation in phase noise.…”

Section: Introductionmentioning

confidence: 99%

“…The reduction of supply voltage in the advanced technologies culminates in lower voltage amplitude that is more vulnerable to small SET induced charges. Furthermore, the smaller capacitances at the nodes existing in CMOS structures cannot protect the nodes of the circuit from voltage variations spring from induced charges [11, 13]. Therefore, the VCO output suffers from signal amplitude, phase and frequency deviations.…”

Section: Introductionmentioning

confidence: 99%

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Fault‐tolerant delay cell for ring oscillator application in 65 nm CMOS technology

Salem

Zandevakili

Mahani

et al. 2018

IET Circuits, Devices & Systems

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A novel fault tolerant delay cell for ring oscillator (RO) is proposed. As RO is one of the crucial blocks in phased locked loop, delayed locked loo and clock data recovery, it should be tolerated against single event transient (SET) and stuck at faults for harsh environment. Their proposed hybrid fault tolerant topology is combination of triple and quad transistors redundancy, which is applied to the delay cell structure based on the sensitivity role of each transistor. The simulation results with Cadence software show that the proposed fault-tolerant delay cell dissipates 34.34 µW power, while it occupies 127.2 µm 2 chip area. The proposed topology not only has lower power dissipation in comparison with existing fault tolerant delay cells but also is more reliable against stuck at single and multiple faults and also SETs. By using the proposed reliable delay cell in the RO, the achieved power dissipation and phase noise are about 249 µW and −96 dBc/Hz, respectively, while higher reliability is achieved in comparison with non-redundant RO s.

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Section: Proposed Fault‐tolerant Delay Cellsmentioning

confidence: 99%

Section: Proposed Fault‐tolerant Delay Cellsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Fault‐tolerant delay cell for ring oscillator application in 65 nm CMOS technology

Salem

Zandevakili

Mahani

et al. 2018

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…Even though the biasing resistor helps to isolate the bias current transistor, the extra voltage drop across the resistor limits the voltage swing. A similar approach was proposed with a distributed bias technique in [14]. TID effects on silicon‐on‐insulator (SOI)‐based VCOs have been examined in [15].…”

Section: Introductionmentioning

confidence: 99%

Single event transient mitigation techniques for a cross‐coupled LC oscillator, including a single‐event transient hardened CMOS LC‐VCO circuit

Karthigeyan¹,

Radha²,

Manikandan

2021

IET Circuits, Devices & Syst

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Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in the sub-100 nm regime in the radiation environment. This study proposes techniques to mitigate SETs in CMOS voltage-controlled oscillators (VCOs) without affecting the circuit specifications. A circuit asymmetry technique is used for faster recovery of the oscillator in the event of a single event transient (SET) caused by an ion hit. Also, a new SET tolerant inductor capacitor-voltage controlled oscillator (LC-VCO) topology is proposed for a radiation environment that shows reduced phase displacement, amplitude displacement, and recovery time. A comparison has been made with various LC-VCOs that have an inherent rad-hard capability which proves a significant improvement in SET sensitivity. K E Y W O R D S radiation hardening (electronics), voltage-controlled oscillatorsThis is an open access article under the terms of the Creative Commons Attribution-NonCommercial License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited and is not used for commercial purposes.

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Design and analysis of radiation-tolerant high frequency voltage controlled oscillator for PLL applications

Rajalingam

Jayakumar

Routray

2021

AEU - International Journal of Electronics and Communications

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Design of SET tolerant LC oscillators using distributed bias circuitry

Cited by 16 publications

References 11 publications

Fault‐tolerant delay cell for ring oscillator application in 65 nm CMOS technology

Fault‐tolerant delay cell for ring oscillator application in 65 nm CMOS technology

Single event transient mitigation techniques for a cross‐coupled LC oscillator, including a single‐event transient hardened CMOS LC‐VCO circuit

Design and analysis of radiation-tolerant high frequency voltage controlled oscillator for PLL applications

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