2023
DOI: 10.1063/5.0169573
|View full text |Cite
|
Sign up to set email alerts
|

Design of SiO2/4H–SiC MOS interfaces by sputter deposition of SiO2 followed by high-temperature CO2-post deposition annealing

Tae-Hyeon Kil,
Takuma Kobayashi,
Takayoshi Shimura
et al.

Abstract: Oxidation of silicon carbide (SiC) is known to induce defects at the interface of the SiO2/SiC system. NO-annealing is a standard industrial method of nitridation, but oxidation may progress during NO-nitridation, which may generate interface defects. Here, we propose a new method of fabricating SiO2/SiC metal-oxide-semiconductor (MOS) devices: sputter deposition of SiO2 in an Ar/N2 gas mixture followed by high-temperature CO2-post deposition annealing to form SiO2 and incorporate nitrogen at the interface whi… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2

Citation Types

0
2
0

Year Published

2024
2024
2024
2024

Publication Types

Select...
1

Relationship

0
1

Authors

Journals

citations
Cited by 1 publication
(2 citation statements)
references
References 27 publications
0
2
0
Order By: Relevance
“…Failure modes in gate oxide include threshold voltage shifts and increased leakage currents [8]. High interface trap density is mentioned as the primary cause of these phenomena [8][9][10][11]. Therefore, there was a variety of research performed to overcome the reliability issue at the 4H-SiC/SiO 2 interface.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…Failure modes in gate oxide include threshold voltage shifts and increased leakage currents [8]. High interface trap density is mentioned as the primary cause of these phenomena [8][9][10][11]. Therefore, there was a variety of research performed to overcome the reliability issue at the 4H-SiC/SiO 2 interface.…”
Section: Introductionmentioning
confidence: 99%
“…Additionally, the paper explores advanced techniques such as nitrogen implantation and wet oxidation processes to passivate near-interface traps and improve the overall electrical quality of the 4H-SiC/SiO 2 interface [12]. These strategies aim to mitigate interface-related challenges and enhance the performance and reliability of 4H-SiC power MOSFETs by addressing critical issues at the SiC/SiO 2 interface [10]. On the other hand, degradation owing to the 4H-SiC/SiO 2 interface becomes more pronounced while the device is operating [7,9].…”
Section: Introductionmentioning
confidence: 99%