Design of Small Area and Low Power Consumption Mask ROM

Abstract

The compact full custom layout design of a 16-Kb mask-programmable CMOS ROM with low power dissipation is introduced in this paper. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 PJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 um 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efriciently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, not only the layout design can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.

Double Latch Pre-Charge Sense Amplifier in Non-Volatile Memory for Wireless Applications

“…If these two amplifiers (in Fig2&Fig3) [5] were to be controlled by an enable signal shown in Fig8, then sensing current can be greatly reduced. Based on the pre-charge sensing method, the majority of the current consumption takes place during the pre-charging of the global bit line, sensing and latched data time.…”

“…This ROM is tailored to minimize current consumption and to chock VDD to operate even down to 0.7 V. Chip area is also critical in this design, so the goal of this design is to optimize layout size of the ROM firstly, then to reduce power dissipation and to improve speed performance without sacrificing other performances. Currently, Semiconductor Manufacturing International Corporation (SMIC) offers ROM [5] at 0.18μm / 0.13μm CMOS technology. Fig9 shows the chip size comparison between the two technology nodes.…”