Design of Static Random-Access Memory Cell for Fault Tolerant Digital System

Yoon, Taekyung; Park, Jihwan; Yoon, Taehwan

doi:10.3390/app122211500

Cited by 3 publications

(2 citation statements)

References 21 publications

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“…The bitlines have a high value of the capacitive load, which in turn offers RC delays. The recent SRAM designs [ 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 ] reported depict the novel device architectures of 6T SRAM with FinFET, Memristor, and Junctionless TFETs, to claim it to be a low-power device. Here, with our proposed sense amplifier design, the power reduction techniques like negative wordline and source biasing were combined and utilized.…”

Section: Proposed Sense Amplifier: Results and Discussionmentioning

confidence: 99%

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

et al. 2023

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We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications.

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Section: Proposed Sense Amplifier: Results and Discussionmentioning

confidence: 99%

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

et al. 2023

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“…The stability of the data that is stored during a write operation may be impacted by changes in temperature, process fluctuations, and other variables, but SRAM cells are particularly susceptible to these effects. Write driver circuits are used to overcome some of these issues and guarantee that the data is accurately written and kept in the SRAM cell [5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

A novel design of collapsed supply and boosted bit-line swing write driver for fast write access 9T SRAM

Ganesh,

Sai Kumar,

Shoukath Vali

et al. 2024

Eng. Res. Express

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This work presents a collapsed supply and boosted bit-line swing (CSBBS) write driver circuit, with the specific goal of enhancing write performance. The write ability of SRAM cells is gravely affected by device parameter variations in deep sub-threshold region of operations. The collapsed supply and boosted bit-line swing are key features aimed at achieving improvements in speed and efficiency during the memory write process. In comparison to conventional, Ultra dynamic scaled supply write (UDSS), Negative charge-boosted bit line (NCBBL), and Reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuits, Proposed collapsed supply and boosted bit-line swing (CSBBS) for 9T SRAM cell has optimized write access delays of 0.74X, 0.41X, 0.32X and 0.21X, improvement in write margin (WM) of 1.51X, 1.34X, 1.22X and 1.12X respectively. The CSBBS Write driver circuit is implemented using custom compiler (Synopsys) through a 28nm BSIM4 model card for bulk CMOS. MC simulation results are monitored on Cosmoscope wave viewer (Synopsys).

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Special Session: Enhancing Reliability in Digital Computing-in-Memory Architectures Through Approximation and Fault Tolerance Methods

Huang,

Hsiao,

Cheng

2024

2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Design of Static Random-Access Memory Cell for Fault Tolerant Digital System

Cited by 3 publications

References 21 publications

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

A novel design of collapsed supply and boosted bit-line swing write driver for fast write access 9T SRAM

Special Session: Enhancing Reliability in Digital Computing-in-Memory Architectures Through Approximation and Fault Tolerance Methods

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