Design of ternary clock generator

Abstract

A ternary clock generator (TCG) is proposed to settle its shortage. The TCG is implemented at the switch level with a simple structure of 24 MOS transistors and simulated at the layout level using the HSPICE software with TSMC 0.18 μm CMOS technology, showing that it works properly. The analyses show that the proposed TCG not only can output a ternary clock of high quality, meeting the clock's design requirements, but also can be fabricated with standard CMOS technology.Introduction: The main drawbacks of binary integrated circuits are the interconnection and pin-out problems, which result in restrictions on placement and routing of chips [1]. Owing to the large informationcarrying capacity of a ternary signal, the ternary digital system has several important advantages over the binary one. For instance, ternary signals increase the information density of logic elements with less memory requirement for a given data length, and reductions in on-chip interconnections and number of pins, thereby reducing the chip area [1][2][3].Moreover, owing to the fundamental physical limitations in the scaling of the CMOS process, such as the heat dissipation problem, short-channel effects, quantum tunnelling and high leakage power, next generation nanoelectronic devices are being developed, such as the resonant tunnelling devices and quantum-dot cellular automata. These devices are often of multiple states and could play a better device in multivalued circuits, rather than binary circuits [4]. To make full use of the next-generation devices, more attention should be paid to multivalued logic. The most efficient multivalued logic, which leads to less product cost and complexity than binary, is the ternary logic [1,2].Ternary flip-flops (TFFs) are the basic elements of ternary digital systems. For further usage of the ternary signal, the TFFs' clock is expected to be ternary as well. Various kinds of TFFs using ternary clocks (TCLKs) were proposed in [5,6]. These TFFs, however, are not sensitive to all the TCLK edges (TEs) with redundant edges. According to [4], the quad-edge-triggered flip-flop based on TCLKs can be designed, which is sensitive to all the four TEs. This contributes to less power consumption. The used TCLKs, however, can be only simulated by a software, but are not generated by actual circuits presently. This means no ternary clock generator (TCG) for practical application is available. The clock is the most important signal of synchronised digital systems, and the TCG shortage will obstruct practical applications of TCLKs. To solve this issue, this Letter proposes a method to generate TCLKs and a TCG is designed at the switch level, which is simple, robust and practical.

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

“…Binary and ternary logic D flip flop designs, shift registers and counters have been discussed and optimized in various published literature [15,18,26,27]. Senseamplifier based flip-flop (SAFF) with transistor count of 18 reduces clock swing as shown in Fig.…”

An optimal gate design for the synthesis of ternary logic circuits

“…Several designs of ternary sequential circuit are presented in [20,21,22]. In ternary D latch structure of [22] A design of ternary clock generator was introduced in [23]. This design uses CMOS and generates a ternary clock using the binary clock generated by the quartz multivibrator.…”

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

“…Sense Amplifier Flip Flop (SAFF) Binary and ternary logic D flip flop designs, shift registers and counters have been discussed and optimized in various published literature[15,18,26,27]. Senseamplifier based flip-flop (SAFF) with transistor count of 18 reduces clock swing as shown in Fig.3(a), has a power efficient sensing stage followed by a cross coupled NAND2 based D latch.…”