Design of time‐interleaved data acquisition system based on Network on Chip

Abstract

In order to solve the existing problems of time‐interleaved data acquisition system's poor scalability, limited acquisition channels, and complicated clock system based on System on Chip(SoC), this work presents a novel method of high‐speed data acquisition based on Network on Chip (NoC) communication architecture and time‐interleaved principle. Six analog‐to‐digital data acquisition resource nodes are hooked up to the NoC according to the unified features of NoC router interface. The data acquisition controller controls the time‐interleaved acquisition's timing sequences and realizes the remote transmission of data through two Gigabit Ethernet resource nodes. Adding timestamp to the collected data of each channel can recover the waveform signal accurately. The experiment results show that the combination of NoC communication architecture and time‐interleaved data acquisition has a certain innovative significance.

Research on Clock Synchronization of Data Acquisition Based on NoC

“…The feasibility of time-interleaved data acquisition using six ADCs with a sampling rate of 250 MHz and a resolution of 8 bits in the NoC system was verified through simulation. Under the architecture of the NoC system designed in this paper, the total sampling rate of data acquisition with the same six sampling points is 1.5 Gbps, far exceeding the 150 Mbps in [7]. The higher the clock synchronization accuracy, the higher the achievable sampling rate.…”

“…[5]. Such problems can be solved by incorporating the network-on-chip (NoC) technology into TI-ADCs [6], so that the sampling rate can be further improved [7].…”

“…Higher sampling rates call for higher synchronization accuracy and lower phase errors between the sampling clocks. Since NoC-based highspeed data acquisition takes the router clock as the ADC sampling clock, high-precision synchronization of ADC sampling clocks can be achieved as long as the router clocks are precisely synchronized [7].…”

3D network-on-chip data acquisition system mapping based on reinforcement learning and improved attention mechanism

“…To overcome these problems, NoC uses routing technology to replace bus structures for communication, thereby overcoming the limitations of traditional SoC. Data acquisition, storage, and transmission IP nodes are designed as resource nodes in a 3D NoC, achieving a high sampling rate and low latency time-interleaved data acquisition system [2].…”