Design of Ultra-High Performance Si TFTs

Abstract

Design considerations for making use of ultra-high performance Si TFTs for future display systems are presented. Careful choice of the thickness and impurity concentration of the TFT channel is important to maximize the breakdown voltage. In the sub-micron regime, a lightly-doped-drain (LDD) structure is needed to suppress drain-induced phenomena. Layout design considerations based on the knowledge on the channel location dependence of device parameters and alignment method of TFT channels to the grain pattern are important to achieve high performance, while avoiding the undesirable effects of grain-boundary defects.

Thin-Film Transistor and Ultra-Large Scale Integrated Circuit: Competition or Collaboration

“…There are several methods being proposed to selectively forming the channel region within the single large grain, [84][85][86] which are potential solutions for the problem. However, in addition to further improve the grain quality, the transistor structure, channel location, and circuit layout need to be optimized 87) before the poly-Si TFT circuit can compete with the ULSIC in speed.…”