Design of wide-band cmos vco for multiband wireless lan applications

Fong, N.; Plouchart, J.-O.; Zamdmer, N.; Liu, Duixian; Wagner, L.; Plett, C.; Tarr, N. G.

doi:10.1109/jssc.2003.814440

Cited by 169 publications

(57 citation statements)

References 10 publications

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“…The phase noise and Figure Of Merit of the system for all standards were summarized in the Table 1. Table 1 shows the simulated values of phase noise and Factor Of Merit (FOM) (using Fong expression [7] ) of the proposed circuit at 1MHz Offset frequency, at the different generated bands. As can be seen in these results, the best phase noise of the proposed multi band circuit is-137dBc at 2.3GHz and the best FOM is -196 dB.…”

Section: Resultsmentioning

confidence: 99%

“…With: C SW1/2 = The equivalent first and second cell capacitance value C var = The varactor capacitance Usually, Figure Of Merit for the VCO is defined as [7] :…”

Section: Synthesizer Based On Ispdpll Associated With a Modified Multmentioning

confidence: 99%

“…Hence [6] proposed that the varactor was controlled by the DC potentials at both of its input terminals to enable the LC VCO yielding a wide tuning range. Fong [7] developed the accumulation MOS varactor to provide wide band tuning capability at a low supply voltage. However, many studies explore the tuning range of LC VCO but may not meet the multi band requirement • An ISPDPLL multi band synthesizer with frequency calculator is proposed herein to achieve a low phase noise with a narrow tuning range for GSM / DCS and WiMax systems (Fig.…”

Section: Introductionmentioning

confidence: 99%

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Inverse Sine Phase Detector Phase Locked Loop Associated with Modified Multi Band LC Quadrature Voltage Controlled Oscillator for Wireless Communication Systems at 0.9, 1.8, 2.4, 3.5 GHz

Abdellaoui¹

2009

American J. of Engineering and Applied Sciences

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Problem statement:In this study and in consequence of the restricted performance of the multi standard wireless receiver utilizing the classical architectures, we proposed and presented a new architecture of multi band wireless receiver based on an Inverse Sine Phase Detector Phase Locked Loop (ISPDPLL) associated with modified multi band LC quadrature Voltage Controlled Oscillator (VCO), supporting GSM/DCS/DECT/Bluetooth/WiMax systems. Approach: To accomplish the multi standard receiving architecture at sufficiently good performance and at a low hardware cost, the proposed circuit, using an ISPDPLL associated with VCO based on switched capacitors utilizing a several numeric controlled capacitive branch and cross-coupled transistors, was implemented in 0.35 µm CMOS technology and designed to yield quadrature output signals (I-Q) allowing to eliminate the dephasing block (90°) employed in a multi band Zero IF architecture receiver, that make the proposed architecture amenable for monolithic integration and 4G multi standard application. Results: This novel system presented high performance and good potentiality to cover perfectly the wireless multi standard receiving on the large band with the same transmission condition. Conclusion/Recommendations: The performance of this system was analyzed and demonstrated to have a minimum phase noise, a good Factor Of Merit (FOM) and wide tuning for these standard applications.

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Section: Resultsmentioning

confidence: 99%

“…With: C SW1/2 = The equivalent first and second cell capacitance value C var = The varactor capacitance Usually, Figure Of Merit for the VCO is defined as [7] :…”

Section: Synthesizer Based On Ispdpll Associated With a Modified Multmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Inverse Sine Phase Detector Phase Locked Loop Associated with Modified Multi Band LC Quadrature Voltage Controlled Oscillator for Wireless Communication Systems at 0.9, 1.8, 2.4, 3.5 GHz

Abdellaoui¹

2009

American J. of Engineering and Applied Sciences

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“…The total power consumption of the S-QVCO is 2.7 mW at 1.8 V power supply. A widely used figure of merit (FOM) for the VCO is defined as [14] { } 20 log( ) 20 log( )…”

Section: Quadrature Voltage-controlled Oscillator (Qvco)mentioning

confidence: 99%

A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4

Krishna

Xie

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Abstract. This paper presents a low power 2.4-GHz fully integrated 1 MHz resolution IEEE 802.15.4 frequency synthesizer designed using 0.18um CMOS technology. An integer-N fully programmable divider employs a novel Truesingle-phase-clock (TSPC) 47/48 prescaler and a 6 bit P and S counters to provide the 1 MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillator (S-QVCO) to generate quadrature signals. The PLL consumes 3.6 mW of power at 1.8 V supply with the fully programmable divider consuming only 600 uW. The S-QVCO consumes 2.8 mW of power with a phase noise of -122dBc/Hz at 1 MHz offset. IntroductionMost of the wireless communication standards prior to IEEE 802.15.4/Zigbee were tailored towards high data rate and multimedia friendly applications. The need for low data rate and low power wireless solutions with emphasis on sensor network applications resulted in the development of IEEE 802.15.4 standard. The recent development and advanced scaling CMOS technologies have made it more attractive to implement a single chip CMOS wireless transceiver featuring both high level of integration and low power consumption [1]. The higher power consumption in the frequency synthesizer is mainly due to the VCO and the first stage divider which is driven by the VCO. The 2.4 GHz synthesizer reported in [2] with a frequency resolution of 5 MHz consumes a power of 7.85 mW at 1.8 V power supply in 0.18 um CMOS technology. Here, the first stage divider is designed using current-mode logic (CML) [6] which consumes a large amount of power. The synthesizer reported in [3] consumes 2.4 mW at 1.2 V supply in 0.13 um CMOS technology. It uses a 16/17 dynamic logic prescaler as first stage divider which consumes only 176 uA at 2.5 GHz and the complete divider is designed with 5

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“…Tuning of the resonant center frequency can be done in a few ways, i.e., by using the varactor, tunable active inductor [12], and switched capacitor array [13,14] or switched inductor array [15]. But all conventional tuning methods have limitations.…”

Section: Switchable Passive Network For Reconfigurable Designmentioning

confidence: 99%

Design of reconfigurable RF front-end for multi-standard receiver using switchable passive networks

Kim¹,

Jang²,

Yoo³

2006

Analog Integr Circ Sig Process

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For successful implementation of a multistandard receiver, a reconfigurable receiver architecture and a reconfigurable component design technique are essential. In this paper, an adaptable receiver architecture and a reconfigurable RF design technique using a switchable passive network are proposed. To verify the proposed design technique, the reconfigurable mixer and QVCO are designed using a flexible matching network and flexible LC tank, respectively. The measurement results of each component well prove the usefulness of the switchable passive network.

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Design of wide-band cmos vco for multiband wireless lan applications

Cited by 169 publications

References 10 publications

Inverse Sine Phase Detector Phase Locked Loop Associated with Modified Multi Band LC Quadrature Voltage Controlled Oscillator for Wireless Communication Systems at 0.9, 1.8, 2.4, 3.5 GHz

Inverse Sine Phase Detector Phase Locked Loop Associated with Modified Multi Band LC Quadrature Voltage Controlled Oscillator for Wireless Communication Systems at 0.9, 1.8, 2.4, 3.5 GHz

A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4

Design of reconfigurable RF front-end for multi-standard receiver using switchable passive networks

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