2018
DOI: 10.15625/2525-2518/51/6/11642
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Design Optimization of Extremely Short-Channel Graded Si/Sige Heterojunction Tunnel Field-Effect Transistors for Low Power Applications

Abstract: This study investigates, by a two-dimensional simulation, the design optimization of a proposed 8 nm tunnel field-effect transistor (TFET) for low standby power (LSTP) applications utilizing graded Si/SiGe heterojunction with device parameters based on the ITRS specifications. The source Ge mole fraction should be designed approximately 0.8 because using lower Ge fractions causes severe short-channel effects while with higher values does not significantly improve the device performance but may create big diffi… Show more

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