Design Optimization of Pillar Bump Structure for Minimizing the Stress in Brittle Low K Dielectric Material Layer

Abstract

Cu pillar bump offers a number of advantages for flip chip packaging, compared to the conventional solder bump. However, due to its rigidity structure, Cu pillar bump introduces a lot of stress to the chip, which causes the failure of packaging structures, especially for the advanced node devices which typically have brittle low K dielectric material. In this paper, for the first time we propose two types of Cu pillar structures to reduce the stress. The first Cu pillar structure has bigger Cu dimensions at the base. The other one is designed to add an additional Cu pad under the Cu pillar bump. Finite element analysis is used to study the stress of the both structures, and it is found that with the increase in pillar bump contact area over the chip surface, the stress decreases in both structures. Results also indicate that the Cu pillar bump undercut induces higher stress, and thin Cu 6 Sn 5 intermetallic compound has less impact on the stress during flip chip mount reflow. The study provides a novel way to improve the reliability by reducing the stress in the Cu pillar bump related packaging.

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Improved GA and Its Application in Performance Optimization of Electronic Components

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