Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

Peng, Yarui; Ku, Bon Woong; Park, Younsik; Park, Kwang-Il; Jang, Seong-Jin; Choi, Jongwan; Lim, Sung Kyu

doi:10.1145/2744769.2744819

Cited by 9 publications

(5 citation statements)

References 6 publications

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“…In [1], different 3D-stacked DRAM package configurations were analyzed and compared from a thermal and power delivery perspectives. In [2], various PDN models were analyzed for various 3D-stacked DRAM architectures (including HMC) that involved replacing TSVs with redistribution layers. In [3], different unit-cell topologies for TSV-based PDNs were analyzed for IR-drop noise characterization in 3D ICs.…”

Section: Related Workmentioning

confidence: 99%

Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs

Bose

Thakkar

2021

Proceedings of the 2021 Great Lakes Symposium on VLSI

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With 3D-stacked DRAM architectures becoming more prevalent, it has become important to find ways to characterize and mitigate the adverse effects that can hinder their inherent access parallelism and throughput. One example of such adversities is the electromigration (EM) effects in the through-silicon vias (TSVs) of the power delivery network (PDN) of 3D-stacked DRAM architectures. Several prior works have addressed the effects of EM in TSVs of 3D integrated circuits. However, no prior work has addressed the effects of EM in the PDN TSVs on the performance and lifetime of 3D-stacked DRAMs. In this paper, we characterize the effects of EM in PDN TSVs on a Hybrid Memory Cube (HMC) architecture employing the conventional PDN design with clustered layout of power and ground TSVs. We then present a new PDN design with a distributed layout of power and ground TSVs and show that it can mitigate the adverse effects of EM on the HMC architecture performance without requiring additional power and ground pins. Our benchmark-driven simulation-based analysis shows that compared to the clustered PDN layout, our proposed distributed PDN layout improves the EM-affected lifetime of the HMC architecture by up to 10 years. During this useful lifetime, the HMC architecture yields up to 1.51× less energy-delay product (EDP).

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Section: Related Workmentioning

confidence: 99%

Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs

Bose

Thakkar

2021

Proceedings of the 2021 Great Lakes Symposium on VLSI

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“…Junwhan Ahn et al [3] proposed an adaptive mechanism to partially disable off-chip links of HMCs to reduce the energy consumption of the off-chip links. Yarui Peng et al [11] presented a cross-domain CAD/architectural platform that addresses DC power noise issues in 3D DRAM targeting stacked DDR3, Wide I/O, and hybrid memory cube technologies.…”

Section: A Hybrid Memory Cubementioning

confidence: 99%

Inexpensive HMC+DRAM Hybrid Main Memory Architecture with LRU-based Data Distribution Management

Zhou

Zhang

Niu

et al. 2016

Proceedings of the 2016 International Conference on Artificial Intelligence: Technologies and Applications

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The Hybrid Memory Cube (HMC) is a 3-D-stacked DRAM architecture whose I/O interface achieves up to 320 GB/s of external bandwidth. Therefore, the HMC is a promising alternative to DDRx memory due to its potential to achieve substantially improved memory bandwidth. However, the high price of a HMC device compromises cost efficiency when the device is lightly utilized. The cost of a HMC device with 2GB capacity is about 5 times of a DDRx memory with the same capacity. In this paper, we propose a new inexpensive HMC+DRAM hybrid main memory architecture to reduce the cost consumption. In order to manage such hybrid memories, we develop a LRU-based data distribution mechanism to determine the destination of particular data flow. Evaluations show that our scheme reduces the cost consumption of Main Memory by 48% on average with a negligible performance degradation compared to a current HMC-based system. Also, our architecture outperforms a current DRAM-based system by 1.5 times, and reduces the response delay by 1.2 times.

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“…PnM enables the design of flexible substrates that support a diverse range of operations. However, the performance, efficiency, and scalability of near-bank PnM architectures [22, 36-38, 42, 43, 51-54, 56, 58] can be limited by design and fabrication challenges, such as 1) the difficulty in designing complex logic due to the limited number of DRAM metal layers [94,95], and 2) the inefficiency of the DRAM process for the implementation of digital logic due to its heavy optimization for memory density [51,54]. In 3D-stacked memories, the logic layer's limited area and thermal budgets impose additional constraints.…”

Section: Introductionmentioning

confidence: 99%

pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables

Ferreira¹,

Falcão

Gómez-Luna³

et al. 2022

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Data movement between the main memory and the processor is a key contributor to execution time and energy consumption in memory-intensive applications. This data movement bottleneck can be alleviated using Processing-in-Memory (PiM). One category of PiM is Processing-using-Memory (PuM), in which computation takes place inside the memory array by exploiting intrinsic analog properties of the memory device. PuM yields high performance and energy efficiency, but existing PuM techniques support a limited range of operations. As a result, current PuM architectures cannot efficiently perform some complex operations (e.g., multiplication, division, exponentiation) without large increases in chip area and design complexity.To overcome these limitations of existing PuM architectures, we introduce pLUTo (processing-using-memory with lookup table (LUT) operations), a DRAM-based PuM architecture that leverages the high storage density of DRAM to enable the massively parallel storing and querying of lookup tables (LUTs). The key idea of pLUTo is to replace complex operations with low-cost, bulk memory reads (i.e., LUT queries) instead of relying on complex extra logic.We evaluate pLUTo across 11 real-world workloads that showcase the limitations of prior PuM approaches and show that our solution outperforms optimized CPU and GPU baselines by an average of 713× and 1.2×, respectively, while simultaneously reducing energy consumption by an average of 1855× and 39.5×. Across these workloads, pLUTo outperforms state-of-the-art PiM architectures by an average of 18.3×. We also show that different versions of pLUTo provide different levels of flexibility and performance at different additional DRAM area overheads (between 10.2% and 23.1%). pLUTo's source code and all scripts required to reproduce the results of this paper are openly and fully available at https://github.com/CMU-SAFARI/pLUTo.

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Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

Cited by 9 publications

References 6 publications

Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs

Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs

Inexpensive HMC+DRAM Hybrid Main Memory Architecture with LRU-based Data Distribution Management

pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables

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