Design Procedure and Selection of TIQ Comparators for Flash ADCs

Abumurad, Abdulrahman; Choi, Kyusun

doi:10.1007/s00034-017-0574-x

Cited by 11 publications

(5 citation statements)

References 21 publications

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“…As mentioned in the previous section, the major challenge in flash ADCs is the comparators and reference voltages of them causing the greatest impact power consumption, area occupation on a chip and limited speed, the second problem is the encoders' delay. Above-mentioned setbacks are conducted in a number of papers [10][11][12][13][14][15][16][17][18][19][20]. In this paper, both the above-mentioned problems are covered and a new flash ADC is presented.…”

Section: Review Of the Structure Flash Adcmentioning

confidence: 99%

“…Another type of the comparator is the TIQ‐based comparator. TIQ‐based comparator does not require any resistor ladder hence it is more power and space efficient [15–20].…”

Section: Proposed Flash Adcmentioning

confidence: 99%

“…The **threshold inverter quantisation (TIQ)-based ADC overcomes these problems. TIQ-based ADC does not require any resistor ladder; hence it is more power and space efficient [15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

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Approach for low power high speed 4‐bit flash analogue to digital converter

Razavi

Tavakoli

Setoudeh

2020

IET Circuits, Devices & Systems

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In this study a new structure was presented to design and simulate a considerably low power and high-speed 4-bit flash analogue to digital converter based on TSMC 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. In this structure, in order to reduce the power consumption in the proposed comparator, the reference voltage was removed and replaced with the threshold voltage of CMOS transistors. This method has reduced the power consumption greatly. Additionally, by employing reversible logic in the 2:1 multiplier, the power consumption and the number of stages were dropped and obtaining a faster converter was considered as the other breakthrough. The simulation was carried out in 1.8 V supply voltage and power consumption of 330 µW while the sampling rate was equal to 2GSample/s.

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Section: Review Of the Structure Flash Adcmentioning

confidence: 99%

“…Another type of the comparator is the TIQ‐based comparator. TIQ‐based comparator does not require any resistor ladder hence it is more power and space efficient [15–20].…”

Section: Proposed Flash Adcmentioning

confidence: 99%

See 1 more Smart Citation

Approach for low power high speed 4‐bit flash analogue to digital converter

Razavi

Tavakoli

Setoudeh

2020

IET Circuits, Devices & Systems

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“…A threshold inverter quantization (TIQ) is a fascinating technique and is very popular in comparator design. There are great choices for TIQ comparators and for how to select them to apply in flash ADCs, which can be found in [ 4 ]. Take articles [ 5 , 6 , 7 , 8 ] as examples, which all discuss this structure when constructing flash ADCs.…”

Section: Introductionmentioning

confidence: 99%

Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process

Thai

Pham

2022

Sensors

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This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.

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“…The five possible process corners are typical (TT), slow-slow (SS), fast-fast (FF), slow-fast (SF) and fast-slow (FS). Transistor threshold voltage variation across process corners [79]. The peak PCE of low-power rectifier is not affected much by temperature variation and delta is in the range of -3.8% (at 90 0 C) to 6.1% (at -40 0 C).…”

Section: Process Variationsmentioning

confidence: 96%

Power management in energy harvesting

Lau¹

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A dual-path wide-power-range rectifier for RF energy harvesting is presented in this thesis. The proposed idea focuses on maximizing efficiency in harvesting energy from the surrounding environment and designated energy source to support wide variety of applications in low power devices' wireless charging. The harvester consists of a low-power rectifier, a high-power rectifier and a voltageaware block. In the low-power rectifier, novel DC-boosted gate bias technique is proposed to enhance power conversion efficiency (PCE) by improving forward peak current, reducing diode forward voltage drop and suppressing reverse leakage current. A novel internal body-biasing technique is proposed in the highpower rectifier to regulate the transistors' threshold voltage (V th ) for optimal efficiency. A voltage-aware block, which consists of a voltage detector, a switch and an adjustable-offset comparator, has been incorporated into the high-power rectification path to minimize overall power consumption.The proposed circuit is fabricated in 65 nm 6M/1P standard CMOS technology.Peak PCE of 70.4% is measured on the low-power rectifier with -5.5 dBm input power at 2.45 GHz when driving a 15 kΩ load. For high-power rectifier, peak PCE of 56.6% is measured with 1.3 dBm input power at 2.45 GHz when driving a 15 kΩ load. The chip has PCE higher than 20% over a 19.8 dB of extended input power range from -13.5 dBm to 6.3 dBm.

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Design Procedure and Selection of TIQ Comparators for Flash ADCs

Cited by 11 publications

References 21 publications

Approach for low power high speed 4‐bit flash analogue to digital converter

Approach for low power high speed 4‐bit flash analogue to digital converter

Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process

Power management in energy harvesting

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