Design SHA-2 MIPS Processor Using FPGA

Abstract

According to the wide developments in the area of communications, there is a demand for secure system for data transmissions. Hence, a new algorithm and security standards are developed. One of these algorithms and standards are the Hash function. In this paper, a Hash system SHA-2 MIPS (Microprocessor without Interlocked Pipelines) Processor (single cycle) is designed using Xilinx Spartan-3AN interfaced with keyboard and Video Graphics Array (VGA) display. The implementation of the MIPS processor by choosing a certain number of instructions that is necessary to invoke the SHA-384 and SHA-512 algorithm. A keyboard is interfaced with the Xilinx Spartan-3AN kit, to enable the user to enter the data and the result is shown on a VGA Display.