Design space exploration and implementation of a high performance and low area Coarse Grained Reconfigurable Processor

Suh, Dongkwan; Kwon, Kiseok; Kim, Sukjin; Ryu, Soojung; Kim, Jeongwook

doi:10.1109/fpt.2012.6412114

Cited by 36 publications

(17 citation statements)

References 10 publications

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“…Second, the feasible design space exploration is typically limited to an architecture baseline or specification format. However, it was not stated clearly in previous works which baseline was used or why the baseline was adopted [66,80,118,119]. If the baseline is not suitable to the target domains, then the process of the design space exploration might converge to a suboptimal solution.…”

Section: Trend 1: Programming-driven Architecture Designmentioning

confidence: 99%

A Survey of Coarse-Grained Reconfigurable Architecture and Design

et al. 2019

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As general-purpose processors have hit the power wall and chip fabrication cost escalates alarmingly, coarsegrained reconfigurable architectures (CGRAs) are attracting increasing interest from both academia and industry, because they offer the performance and energy efficiency of hardware with the flexibility of software. However, CGRAs are not yet mature in terms of programmability, productivity, and adaptability. This article reviews the architecture and design of CGRAs thoroughly for the purpose of exploiting their full potential. First, a novel multidimensional taxonomy is proposed. Second, major challenges and the corresponding state-of-the-art techniques are surveyed and analyzed. Finally, the future development is discussed. CCS Concepts: • Computer systems organization → Reconfigurable computing; • Hardware → Reconfigurable logic and FPGAs; • Theory of computation → Models of computation;

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Section: Trend 1: Programming-driven Architecture Designmentioning

confidence: 99%

A Survey of Coarse-Grained Reconfigurable Architecture and Design

et al. 2019

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“…A representative example of CGRA architecture is ADRES [47] that tightly couples a VLIW (very- long instruction word) processor with coarse-grained reconfigurable matrix. A variation of ADRES architecture has been introduced commercially as Samsung Reconfigurable Processor (SRP) [70] as part of the mobile application processor systemon-chip. The SRP consists of sixteen FUs, one or two register files, four load/store units, scratch pad memory (SPM), an instruction cache for VLIW mode and configuration memory for CGRA.…”

Section: Coarse-grained Reconfigurable Arrays (Cgras)mentioning

confidence: 99%

Heterogeneous Multi-core Architectures

Mitra

2015

IPSJ Transactions on System LSI Design Methodology

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Transistor count continues to increase for silicon devices following Moore's Law. But the failure of Dennard scaling has brought the computing community to a crossroad where power has become the major limiting factor. Thus future chips can have many cores; but only a fraction of them can be switched on at any point in time. This dark silicon era, where significant fraction of the chip real estate remains dark, has necessitated a fundamental rethinking in architectural designs. In this context, heterogeneous multi-core architectures combining functionality and performance-wise divergent mix of processing cores (CPU, GPU, special-purpose accelerators, and reconfigurable computing) offer a promising option. Heterogeneous multi-cores can potentially provide energy-efficient computation as only the cores most suitable for the current computation need to be switched on. This article presents an overview of the state-of-the-art in heterogeneous multi-core landscape.

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“…Over the past 15 years, many CGRA processors with different architectures and execution modes have been proposed [4,5,11,13,16,17,29,31,39,43,46]. In this work, we focus on CGRAs that execute modulo-scheduled loop kernels and operate in dataflow mode [5,31,46]. The dataflow graph (DFG) of a loop kernel is mapped onto such CGRAs in the form of a modulo schedule, a variant of a software-pipelined loop.…”

Section: Introductionmentioning

confidence: 99%

Improving Energy Efficiency of Coarse-Grain Reconfigurable Arrays Through Modulo Schedule Compression/Decompression

Lee

Moghaddam

Suh

et al. 2018

ACM Trans. Archit. Code Optim.

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Modulo-scheduled course-grain reconfigurable array (CGRA) processors excel at exploiting loop-level parallelism at a high performance per watt ratio. The frequent reconfiguration of the array, however, causes between 25% and 45% of the consumed chip energy to be spent on the instruction memory and fetches therefrom. This article presents a hardware/software codesign methodology for such architectures that is able to reduce both the size required to store the modulo-scheduled loops and the energy consumed by the instruction decode logic. The hardware modifications improve the spatial organization of a CGRA's execution plan by reorganizing the configuration memory into separate partitions based on a statistical analysis of code. A compiler technique optimizes the generated code in the temporal dimension by minimizing the number of signal changes. The optimizations achieve, on average, a reduction in code size of more than 63% and in energy consumed by the instruction decode logic by 70% for a wide variety of application domains. Decompression of the compressed loops can be performed in hardware with no additional latency, rendering the presented method ideal for low-power CGRAs running at high frequencies. The presented technique is orthogonal to dictionary-based compression schemes and can be combined to achieve a further reduction in code size. CCS Concepts: • Computer systems organization → Reconfigurable computing; • Hardware → Power estimation and optimization; • Software and its engineering → Compilers;

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Design space exploration and implementation of a high performance and low area Coarse Grained Reconfigurable Processor

Cited by 36 publications

References 10 publications

A Survey of Coarse-Grained Reconfigurable Architecture and Design

A Survey of Coarse-Grained Reconfigurable Architecture and Design

Heterogeneous Multi-core Architectures

Improving Energy Efficiency of Coarse-Grain Reconfigurable Arrays Through Modulo Schedule Compression/Decompression

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