Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip

Das, Sourav; Doppa, Janardhan Rao; Pande, Partha Pratim; Chakrabarty, Krishnendu

doi:10.1109/tcad.2016.2604288

Cited by 64 publications

(36 citation statements)

References 38 publications

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“…Conventional 2D architectures, such as mesh NoCs, cannot efficiently handle this many-to-few traffic or fulfill the quality of service (QoS) requirements for both CPU and GPU communication [7]. In recent years, designers have taken advantage of 3D IC's higher packing density and lower interconnect latency to improve the performance of manycore systems [4], [5]. The advantages of 3D integration for CPU and GPU based manycore systems have been demonstrated in [16], [17] where the authors have principally focused on improving the throughput and energy efficiency by using the benefits of 3D integration for homogeneous systems (all CPUs or all GPUs) only.…”

Section: D Heterogeneous Nocsmentioning

confidence: 99%

“…To further reduce data transfer costs, three-dimensional (3D) integrated circuits (ICs) have been investigated as a possible solution and have made significant strides towards improving communication efficiency [4], [5]. By connecting planar dies stacked on top of each other with through-silicon vias (TSVs), the communication latency, throughput, and energy consumption can be further improved [6].…”

Section: Introductionmentioning

confidence: 99%

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Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems

Joardar

Kim

Doppa

et al. 2019

IEEE Trans. Comput.

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The rising use of deep learning and other big-data algorithms has led to an increasing demand for hardware platforms that are computationally powerful, yet energy-efficient. Due to the amount of data parallelism in these algorithms, high-performance threedimensional (3D) manycore platforms that incorporate both CPUs and GPUs present a promising direction. However, as systems use heterogeneity (e.g., a combination of CPUs, GPUs, and accelerators) to improve performance and efficiency, it becomes more pertinent to address the distinct and likely conflicting communication requirements (e.g., CPU memory access latency or GPU network throughput) that arise from such heterogeneity. Unfortunately, it is difficult to quickly explore the hardware design space and choose appropriate tradeoffs between these heterogeneous requirements. To address these challenges, we propose the design of a 3D Networkon-Chip (NoC) for heterogeneous manycore platforms that considers the appropriate design objectives for a 3D heterogeneous system and explores various tradeoffs using an efficient machine learning (ML)-based multi-objective optimization (MOO) technique. The proposed design space exploration considers the various requirements of its heterogeneous components and generates a set of 3D NoC architectures that efficiently trades off these design objectives. Our findings show that by jointly considering these requirements (latency, throughput, temperature, and energy), we can achieve 9.6% better Energy-Delay Product on average at nearly iso-temperature conditions when compared to a thermally-optimized design for 3D heterogeneous NoCs. More importantly, our results suggest that our 3D NoCs optimized for a few applications can be generalized for unknown applications as well. Our results show that these generalized 3D NoCs only incur a 1.8% (36-tile system) and 1.1% (64-tile system) average performance loss compared to application-specific NoCs.

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Section: D Heterogeneous Nocsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems

Joardar

Kim

Doppa

et al. 2019

IEEE Trans. Comput.

Self Cite

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“…Once a core is selected for a given task, the task delay is recalculated to reflect the new changes due to the impact of process and voltage variations on the selected core. XYZ-routing is used to handle data traffic [29], [61].…”

Section: -Children-slack Task Priority or Cstp: After Randommentioning

confidence: 99%

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

et al. 2019

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In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-V dd /frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power optimization methods including within-die process and workload variations. LVSiM provides a holistic platform for multi-V dd /frequency voltage island analysis, optimization, and design. It provides a tool for the early design exploration stage to analyze large-scale manycores with a given number of cores on 3D-stacked layers, network-on-chip communication busses, technology parameters, voltage and frequency values, and power grid parameters, using a variety of different optimization methods. LVSiM has been calibrated with Sniper/McPAT at a nominal frequency, and then the energy-delay-product (EDP) numbers were compared after frequency scaling. The average error is shown to be 10% after frequency scaling, which is sufficient for our purposes. The experiments in this work are carried out for different Idle/Dynamic ratios considering 1260 benchmarks with task sizes ranging from 4000 to 16 000 executing on 3200 cores. The best configurations are shown to produce on average 20.7% to 24.6% EDP savings compared to the nominal configuration. Traditional scheduling methods are used in the nominal configuration with the unused cores switched off. In addition, we show that, as the Idle/Dynamic ratio increases, the multi-V dd /frequency approach becomes less effective. In the case of a high Idle/Dynamic ratio, the minimum EDP can be achieved through switching off unused cores as opposed to using a multi-V dd /frequency approach. This conclusion is important, especially in the dark-silicon era, where switching cores on and/or off as needed is a common practice.

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“…Exploration means collecting new information whereas the exploitation means using the existing information for communication among different individuals of the swarms to better manage their coordination. During solving the optimization problems, the exploration is the process of increasing the solution search space to bring variations in the values of optimization function (collecting new information) [30] whereas the exploitation means focusing on the so far found solutions to check all the nearby solutions to enable the search space to not skip the most optimal solution present in the local solution search space (using the existing information) [31].…”

Section: Introductionmentioning

confidence: 99%

An Enhanced Firefly Algorithm Using Pattern Search for Solving Optimization Problems

et al. 2020

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Firefly Algorithm (FA) is one of the most recently introduced stochastic, nature-inspired, meta-heuristic approaches used for solving optimization problems. The conventional FA use randomization factor during generation of solution search space and fireflies position changing, which results in imbalanced relationship between exploration and exploitation. This imbalanced relationship causes in incapability of FA to find the most optimum values at termination stage. In the proposed model, this issue has been resolved by incorporating PS at the termination stage of standard FA. The optimized values obtained from the FA are set as the initial starting points for the PS algorithm and the values are further optimized by PS to get the most optimal values or at least better values than the values obtained by conventional FA during its maximum number of iterations. The performance of the newly developed FA-PS model has been tested on eight minimization functions and six maximization functions by considering various performance evaluation parameters. The results obtained have been compared with other optimization algorithms namely genetic algorithm (GA), standard FA, artificial bee colony (ABC), ant colony optimization (ACO), differential equations (DE), bat algorithm (BA), grey wolf optimization (GWO), Self-Adaptive Step Firefly Algorithm (SASFA), and FA-Cross algorithm in terms of convergence rate and various numerical performance evaluation parameters. A significant improvement has been observed in the solution quality by embedding PS in the standard FA at the termination stage. The result behind this improvement is the better exploration and exploitation of the solution search space at this stage.

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Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip

Cited by 64 publications

References 38 publications

Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems

Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

An Enhanced Firefly Algorithm Using Pattern Search for Solving Optimization Problems

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